74LVX573MTCX Fairchild Semiconductor, 74LVX573MTCX Datasheet

IC LATCH OCTAL LV 3STATE 20TSSOP

74LVX573MTCX

Manufacturer Part Number
74LVX573MTCX
Description
IC LATCH OCTAL LV 3STATE 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Type
D-Typer
Datasheet

Specifications of 74LVX573MTCX

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
5.9ns
Current - Output High, Low
4mA, 4mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Logic Family
LVX
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
CMOS
Package Type
TSSOP
Propagation Delay Time
22ns
Operating Supply Voltage (typ)
2.5/3.3V
High Level Output Current
-4mA
Low Level Output Current
4mA
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Number Of Circuits
8
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVX573MTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
© 2005 Fairchild Semiconductor Corporation
74LVX573M
74LVX573SJ
74LVX573MTC
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Order Number
Package Number
MTC20
IEEE/IEC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011616
Features
Connection Diagram
Pin Descriptions
D
LE
OE
O
Input voltage translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
0
0
–D
–O
Pin Names
7
7
Package Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
June 1993
Revised April 2005
Description
www.fairchildsemi.com

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74LVX573MTCX Summary of contents

Page 1

... Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbols IEEE/IEC © 2005 Fairchild Semiconductor Corporation Features Input voltage translation from Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and ...

Page 2

Functional Description The LVX573 contains eight D-type latches. When the enable (LE) input is HIGH, data on the D n latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. Input Voltage ( Output Diode Current ( 0. 0.5V ...

Page 4

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation 2.7 PLH t Delay Time PHL 3.3 0 Propagation 2.7 PLH t Delay Time PHL 3.3 0 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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