74LVX373MTCX Fairchild Semiconductor, 74LVX373MTCX Datasheet

IC LATCH TRANSP OCT 3ST 20TSSOP

74LVX373MTCX

Manufacturer Part Number
74LVX373MTCX
Description
IC LATCH TRANSP OCT 3ST 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Type
D-Typer
Datasheet

Specifications of 74LVX373MTCX

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
6ns
Current - Output High, Low
4mA, 4mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Logic Family
LVX
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
CMOS
Package Type
TSSOP
Propagation Delay Time
22ns
Operating Supply Voltage (typ)
2.5/3.3V
High Level Output Current
-4mA
Low Level Output Current
4mA
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74LVX373M
74LVX373SJ
74LVX373MTC
74LVX373
Low Voltage Octal Transparent Latch with
3-STATE Outputs
General Description
The LVX373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The latches appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state. The inputs tolerate
up to 7V allowing interface of 5V systems to 3V systems.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Logic Symbols
Connection Diagram
Order Number
Package Number
MTC20
IEEE/IEC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011613
Features
Pin Descriptions
Truth Table
H
L
Z
X
O
D
LE
OE
O
0
Input voltage translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
0
0
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
–D
–O
Previous O
Pin Names
LE
X
H
H
L
7
7
Package Description
0
before HIGH-to-LOW transition of Latch Enable
Inputs
OE
H
L
L
L
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
June 1993
Revised April 2005
D
H
X
L
X
Description
n
www.fairchildsemi.com
Outputs
O
O
Z
H
L
n
0

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74LVX373MTCX Summary of contents

Page 1

... Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDED J-STD-020B. Logic Symbols IEEE/IEC Connection Diagram © 2005 Fairchild Semiconductor Corporation Features Input voltage translation from Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and ...

Page 2

Functional Description The LVX373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this con- n dition the latches are transparent, i.e., a latch ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. Input Voltage ( Output Diode Current ( 0. 0.5V ...

Page 4

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation Delay Time 2.7 PLH PHL 3.3 0.3 t Propagation Delay Time 2.7 PLH PHL n r 3.3 0.3 t ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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