PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 

Specifications of PIC16F684-ISL

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PIC16F684
10.5
Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(64 ms
duration)
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
• Power Glitch
• Software Malfunction
TABLE 10-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address
Name
Bit 7
Bit 6
0Bh/8Bh
INTCON
GIE
PEIE
0Ch
PIR1
EEIF
ADIF
8Ch
PIE1
EEIE
ADIE
9Ah
EEDAT
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
9Bh
EEADR
EEADR7 EEADR6 EEADR5 EEADR
9Ch
EECON1
(1)
9Dh
EECON2
EEPROM Control register 2
Legend:
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
Note 1:
EECON2 is not a physical register.
DS41202C-page 74
10.6
Data EEPROM Operation During
Code-Protect
Data memory can be code-protected by programming
the CPD bit in the Configuration Word register
(Register 12-1) to ‘0’.
prevents
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which
outputs
Programming unused locations in program memory to
‘0’ will also help prevent data memory code protection
from becoming breached.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T0IE
INTE
RAIE
T0IF
INTF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE TMR1IE 0000 0000 0000 0000
EEADR
EEADR
EEADR
WRERR
WREN
Preliminary
the
contents
of
data
memory.
Value on
Value on
Bit 0
all other
POR, BOD
Resets
RAIF
0000 0000 0000 0000
EEADR
0000 0000 0000 0000
WR
RD
---- x000 ---- q000
---- ---- ---- ----
 2004 Microchip Technology Inc.