SCD240110QCM Intel, SCD240110QCM Datasheet
SCD240110QCM
Specifications of SCD240110QCM
Related parts for SCD240110QCM
SCD240110QCM Summary of contents
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... The CD2401 is based on a proprietary, on-chip RISC processor that performs all the time- critical, low-level tasks that are otherwise normally performed by the host system. The CD2401 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and- forget’ ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Features ......................................................................................................................... 9 1.1 Benefits ...............................................................................................................11 1.2 CD2XXX Family Compatibility.............................................................................11 2.0 Conventions ...............................................................................................................13 3.0 Pin Information 3.1 Pin Diagram ........................................................................................................15 3.2 Pin Functions.......................................................................................................16 3.3 Pin Descriptions ..................................................................................................16 4.0 Register Table 4.1 Memory Map .......................................................................................................21 4.1.1 Global Registers.....................................................................................21 4.1.2 ...
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CD2401 — Multi-Protocol Communications Controller 5.4.2 DMA Data Transfer ................................................................................ 45 5.4.3 Bus Error Handling................................................................................. 46 5.4.4 A and B Buffers and Chaining ................................................................ 47 5.4.5 Transmit DMA Transfer .......................................................................... 48 5.4.6 Synchronous Transmitter Examples ...................................................... 49 5.4.7 Receive DMA ...
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Channel Mode Register (CMR) ..............................................................93 8.2.2 Channel Option Register 1 (COR1)........................................................94 8.2.3 Channel Option Register 2 (COR2)........................................................96 8.2.4 Channel Option Register 3 (COR3)......................................................100 8.2.5 Channel Option Register 4 (COR4)......................................................104 8.2.6 Channel Option Register 5 (COR5)......................................................105 8.2.7 Channel Option Register ...
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CD2401 — Multi-Protocol Communications Controller 10.0 Package Specifications 11.0 Ordering Information Example Index ....................................................................................................................................... 169 Bit Index ....................................................................................................................................... 173 Figures 1 Functional Block Diagram ................................................................................... 11 2 Host Read Cycle ................................................................................................. 36 3 Host Write Cycle ................................................................................................. 37 4 Interrupt ...
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SSPC[x] Settings.................................................................................................73 15 SCdet[x] Settings.................................................................................................74 16 Bisync Receive State Transition..........................................................................82 17 Description of States ...........................................................................................83 18 ETC Byte Sequence............................................................................................84 19 Byte Format — ETC Bit Set ................................................................................86 Datasheet Multi-Protocol Communications Controller — CD2401 7 ...
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CD2401 — Multi-Protocol Communications Controller Revision History Revision Date 1.0 5/01 8 Description Initial release. Datasheet ...
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Features • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. (@ CLK 35 MHz) • Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels • 32-bit address, 16-bit data, double-buffered DMA ...
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CD2401 — Multi-Protocol Communications Controller Bisync Features • Programmable for ASCII or EBCDIC encoding • Support for transparent Bisync • Recognition of all special characters enabling: — Block separation — CRC generation and validation • Chaining of long receive blocks ...
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Benefits • Substantially reduced host CPU overhead resulting in more channels and faster overall throughput • No time-critical host software enabling faster and easier software development • Smallest possible footprint for multi-channel device Figure 1. Functional Block Diagram HOST ...
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CD2401 — Multi-Protocol Communications Controller Features Number of modem leads (per channel, including RxD and TxD) On-chip timers UNIX character processing Automatic in-band Rx flow control Special character Tx and recognition Package System interface Pin compatibility NOTES: 1. indicates identical ...
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Conventions Abbreviations Symbol Kbit kbits/sec., kbps Kbyte kbytes/sec. kHz k Mbyte MHz The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ ...
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CD2401 — Multi-Protocol Communications Controller Acronyms Acronym AC alternating current BCC block check character BRG bit rate generator bisync byte synchronous CMOS complementary metal-oxide semiconductor 1 CRC cyclic redundancy check DC direct current DCE data communication equipment DMA direct-memory access ...
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Pin Information 3.1 Pin Diagram RXCIN[3] 51 TXCIN[3] 52 DSR*[0] 53 CTS*[0] 54 TXCOUT/DTR*[0] 55 RTS*[0] 56 DSR*[1] 57 CTS*[1] 58 TXCOUT/DTR*[1] 59 RTS*[1] 60 DSR*[2] 61 GND 62 CTS*[2] 63 TXCOUT/DTR*[2] 64 RTS*[2] 65 DSR*[3] 66 CTS*[3] 67 ...
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CD2401 — Multi-Protocol Communications Controller 3.2 Pin Functions A[7:0] A/D[15:0] CLK CS* AS* DS* R/W* DTACK* SIZ[1:0] BUSCLK BERR* RESET* TEST ADLD* AEN* DATDIR* DATEN* BYTESWAP IACKIN* IACKOUT* IREQ*[3:1] BR* BGIN* BGOUT* BGACK* 3.3 Pin Descriptions The following conventions are ...
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Table 1. Pin Descriptions (Sheet Pin Symbol Type Number CS* 1 AS* 14 I/O (TS) DS* 15 I/O (TS) R/W* 13 I/O (TS) DTACK* 16 I/O (OD) SIZ[0– I/O (TS) IACKIN* 17 Datasheet Multi-Protocol Communications ...
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CD2401 — Multi-Protocol Communications Controller Table 1. Pin Descriptions (Sheet Pin Symbol Type Number IACKOUT* 19 IREQ*[1–3] 21, 23, 24 I/O (OD) BR* 7 BGIN* 9 BGOUT* 10 BGACK* 12 I/O (OD) BERR* 100 A[0–7] 71–78 I/O ...
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Table 1. Pin Descriptions (Sheet Pin Symbol Type Number TEST 33 56, 60, 65, RTS*[0–3] 69 TXCOUT/DTR* 55, 59, 64, [0–3] 68 25, 32, 37, RXCOUT[0–3] 47 54, 58, 63, CTS*[0–3] 67 CD*[0–3] 85, 11, 18, 22 ...
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... BYTESWAP: This pin alters the byte ordering of data during certain 16-bit transfers and changes the half of the data bus on which byte transfers are made to comply with Intel or Motorola processor systems. BYTESWAP does not alter the bus handshake signals. When the BYTESWAP pin is high, the byte of A/D[7:0] precedes that of A/D[15: string of transmit or receive bytes ...
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... The following notes are applicable for NOTES: 1. Address mode G: Global register — one set is always accessible. Address mode P: Per-Channel register — four sets, one per channel, accessible thgough CAR or interrupt context. 2. INT address for Intel-style processor. 3. MOT address for Motorola-style processor. 4.1.1 Global Registers Name ...
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CD2401 — Multi-Protocol Communications Controller 4.1.2 Option Registers Name Description CMR Channel Mode Register COR1 Channel Option Register 1 COR2 Channel Option Register 2 COR3 Channel Option Register 3 COR4 Channel Option Register 4 COR5 Channel Option Register 5 COR6 ...
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Channel Command and Status Registers Name Description CCR Channel Command Register STCR Special Transmit Command Register CSR Channel Status Register MSVR-RTS Modem Signal Value Registers MSVR-DTR 4.1.5 Interrupt Registers Name Description LIVR Local Interrupt Vector Register IER Interrupt Enable ...
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CD2401 — Multi-Protocol Communications Controller 4.1.5.2 Transmit Interrupt Registers Name Description TPILR Transmit Priority Interrupt Level Register TIR Transmit Interrupt Register TISR Transmit Interrupt Status Register TFTC Transmit FIFO Transfer Count TDR Transmit Data Register TEOIR Transmit End Of Interrupt ...
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DMA Receive Registers Name Description ARBADRL A Receive Buffer Address Lower ARBADRU A Receive Buffer Address Upper BRBADRL B Receive Buffer Address Lower BRBADRU B Receive Buffer Address Upper ARBCNT A Receive Buffer Byte Count BRBCNT B Receive Buffer ...
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CD2401 — Multi-Protocol Communications Controller 4.1.7 Timer Registers Name Description TPR Timer Period Register RTPR Receive Timeout Period Register RTPRl Receive Timeout Period Register low RTPRh Receive Timeout Period Register high GT1 General Timer 1 GT1l General Timer 1 low ...
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Asynchronous/Bisync/X.21 Modes Parity ParM1 ParM0 Channel Option Register 2 (COR2) HDLC Mode 0 FCSApd 0 Asynchronous Mode IXM TxlBE ETC Bisync Mode LRC BCC EBCDIC X.21 Mode Channel Option Register 3 (COR3) HDLC/Bisync Mode sndpad Alt1/S55 FCSPre ...
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CD2401 — Multi-Protocol Communications Controller Channel Option Register 5 (COR5) DSRod CDod CTSod Channel Option Register 6 (COR6) Asynchronous Mode IgnCR ICRNL INLCF Bisync Mode X.21 Mode Channel Option Register 7 (COR7) Asynchronous Mode IStrip LNE FCErr Special Character Register ...
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Bit Rate and Clock Option Registers Receive Bit Rate Period Register (RBPR) Receive Clock Option Register (RCOR) TLVal res DpllEn Transmit Bit Rate Period Register (TBPR) Transmit Clock Option Register (TCOR) ClkSel2 ClkSel1 ClkSel0 4.2.4 Channel Command and Status ...
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CD2401 — Multi-Protocol Communications Controller Asynchronous Mode RxEn RxFloff RxFlon Bisync Mode RxEn RxITB RxFrame X.21 Mode RxEn 0 RxSpc Modem Signal Value Registers (MSVR) Modem Signal Value Registers (MSVR-RTS) Modem Signal Value Registers (MSVR-DTR) DSR CD CTS Interrupt Registers ...
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Receive Interrupt Status Register (RISR) Receive Interrupt Status Register low (RISRl) HDLC Mode 0 EOF RxAbt Asynchronous Mode Timeout SCdet2 SCdet1 Bisync Mode 0 EOF RxAbt X.21 Mode LVal SCdet2 SCdet1 Receive Interrupt Status Register high (RISRh) Berr EOF EOB ...
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CD2401 — Multi-Protocol Communications Controller Transmit Interrupt Status Register (TISR) Berr EOF EOE Transmit FIFO Transfer Count (TFTC Transmit Data Register (TDR Transmit End Of Interrupt Register (TEOIR) TermBuff EOF SetTm2 4.2.4.3 Modem/Timer Interrupt ...
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DMA Receive Registers A Receive Buffer Address Lower (ARBADRL) A Receive Buffer Address Upper (ARBADRU) B Receive Buffer Address Lower (BRBADRL) B Receive Buffer Address Upper (BRBADRU) A Buffer Receive Byte Count (ARBCNT) B Buffer Receive Byte Count (BRBCNT) ...
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CD2401 — Multi-Protocol Communications Controller Receive Timeout Period Register high (RTPRh) General Timer 1 (GT1) General Timer 1 low (GT1l) General Timer 1 high (GT1h) General Timer 2 (GT2) Transmit Timer Register (TTR Binary Value, bits 15:8 28 ...
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Functional Description 5.1 Host Interface The CD2401 is a synchronous device with an asynchronous bus interface. A stable input clock is required on the CLK pin — nominally 33 MHz. CLK is divided by two internally, and the resulting ...
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CD2401 — Multi-Protocol Communications Controller Figure 2. Host Read Cycle CS* DS* R/W* A/D[15:0] A[7:0], SIZ[1:0] DTACK* DATEN* DATDIR* 36 DOUT Datasheet ...
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Figure 3. Host Write Cycle CS* DS* R/W* A/D[15:0] A[7:0], SIZ[1:0] DTACK* DATEN* DATDIR* 5.1.2 Byte and Word Transfers Data can be moved to and from the CD2401 in either byte or word transfers. To accommodate various families of host ...
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CD2401 — Multi-Protocol Communications Controller 5.2.1 Contexts and Channels The registers in the CD2401 are grouped into Global, Virtual, and four sets of Per-Channel registers. The CD2401 is normally in the background context, where the CAR selects the channel number ...
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Figure 4. Interrupt Acknowledge Cycle IREQn* IACKIN* DS* R/W*, CS* A/D[15:0] A[7:0] DTACK* DEN* DATDIR* 1 Interrupt vector is always on A/D[7:0]. 5.2.3 Groups and Types There are two general reasons for the CD2401 to request service from the host ...
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CD2401 — Multi-Protocol Communications Controller Interrupt Vector LSBs 00 Receive exception 01 Modem signal change or timer event 10 Transmit data or exception 11 Receive Good Data 40 Datasheet ...
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Table 2. Transmit and Receive Interrupt Service Requests Interrupt Cause Async Receive Good Data BREAK detect Framing error Parity error Receive timeout, no data Special character match Transmitter empty Tx FIFO threshold Receive overrun Clear detect CRC error Residual bit ...
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CD2401 — Multi-Protocol Communications Controller Highest priority: Receive Interrupt register Transmit Interrupt register Lowest priority: Modem Interrupt register 5.2.4.2 Systems with Interrupt Controllers Some systems use an interrupt controller that supplies its own vector during the interrupt acknowledge cycle. To ...
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When an interrupt request line is asserted, the Fair bit for that type of interrupt on the asserting device is cleared. The Fair bit remains cleared until the interrupt line returns to a high state. The CD2401 does not assert ...
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CD2401 — Multi-Protocol Communications Controller 5.3.4 Timers in Synchronous Protocols In synchronous protocols, the timers have no special significance for the CD2401; they are available to support the protocols. They are started by host commands or by interrupts generated by ...
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The CD2401 can perform DMA operations in any of the supported line protocols. A special Append mode feature can reduce host CPU overhead for asynchronous data streams. DMA operations are channel- and direction-specific. In each channel, either the transmitter, the ...
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CD2401 — Multi-Protocol Communications Controller Figure 5. Bus Acquisition Cycle BR* BGIN* BGACK* Another component owns the bus and gives it up here. The CD2401 owns the bus at this point. Figure 6. Data Transfer Timing ADLD* AEN* DATDIR* AS* ...
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If there is a non-zero value in the BERCNT register, the register is decremented and the failed transfer is retried automatically. If the BERCNT is zero, a bus error interrupt is generated and DMA transfers are suspended on the failing ...
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CD2401 — Multi-Protocol Communications Controller 5.4.5 Transmit DMA Transfer As in receive data transfers, two buffers are available for DMA transmit transfers. The A/ † BTBADR and A/BTBCNT registers contain the start address of and the byte count in the ...
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Figure 7. Transmitter A and B Buffers CD2401 TRANSMIT DMA REGISTERS ATBADR (32) ATBCNT (16) ATBSTS (8) (Status Register) TABADR (32) (Currently using Buffer A) BTBADR (32) BTBCNT (16) BTBSTS (8) (Status Register) NOTE: The number of bits in each ...
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CD2401 — Multi-Protocol Communications Controller 7. The CD2401 optionally interrupts the host, with EOF and EOB (TISR[6:5]) both set to indicate that the transmission is complete, and there was no chaining. Example 2 Transmit out of channel 0, and chain ...
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When the CD2401 completes transmission, any necessary CRCs and ending frame delimiters are transmitted. 16. The CD2401 optionally interrupts the host with EOF and EOB set (TISR[6:5]) to indicate that the transmission is complete, and this is the last ...
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CD2401 — Multi-Protocol Communications Controller Figure 8. Receiver A and B Buffers CD2401 TRANSMIT DMA REGISTERS ARBADR (32) ARBCNT (16) ARBSTS (8) (Status Register) RCBADR (32) (Currently using Buffer A) BRBADR (32) BRBCNT (16) BRBSTS (8) (Status Register) NOTE: The ...
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Example 2 Receive a frame on channel 0, which consists of three buffers chained together. The frame is 240-bytes long, and the maximum buffer size is 100. 1. The host checks the Nrbuf bit (DMABSTS[1]) for channel 0 to determine ...
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CD2401 — Multi-Protocol Communications Controller 5.4.7.1 Buffer Allocation The CD2401 contains two DMA descriptors that can be loaded by the CPU to specify transmit buffers. These descriptors are designated A and B, and each consists of a 32-bit address (A/ ...
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Figure 9. DMA Transmit Buffer Selection Update Descriptor and Set 2401own N More Data to Send ? Datasheet Multi-Protocol Communications Controller — CD2401 Start Read DMABSTS to Determine Next Transmit Buffer (NtBuf) Next Buffer 0 1 2401own Bit ? Y ...
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CD2401 — Multi-Protocol Communications Controller 5.4.7.4 Append Mode The Append mode reduces the CPU overhead required to provide asynchronous terminal echoing functionality; this is also necessary for any similar application that involves an unpredictable data stream. The A buffer can ...
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The CPU has the following five options: 1. Terminate the buffer. 2. Discard the exception. 3. Terminate the buffer and discard the exception. 4. Continue from the current position in the buffer. 5. Leave an ‘n’-byte gap in the buffer ...
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CD2401 — Multi-Protocol Communications Controller To retry the buffer from the failure point, the CPU should set the 2401own bit (A/BRBSTS[0]); the CPU should not set the TermBuff bit when writing to REOIR at the end of the interrupt. This ...
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The receive bit rate generator can also be programmed to act as a DPLL. In that mode, the clock select and divisor are programmed near as possible to the nominal receive bit rate. Clock phase adjustments are ...
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CD2401 — Multi-Protocol Communications Controller Figure 10. BRG and DPLL System Clock 8 Clk 0 32 Clk 1 128 Clk 2 512 Clk 3 2048 Clk 4 RXCin or TXCin RX bit clk (for TX BRG only) Receive Clock Option ...
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Table 4. Clock Source Select (Sheet ClkSel2 ClkSel1 Table 5. Bit Rate Constants, CLK = 20 MHz Bit Rate 50 110 150 300 600 1200 2401 3600 4800 7200 9600 19200 ...
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CD2401 — Multi-Protocol Communications Controller Table 6. Bit Rate Constants, CLK = 25 MHz (Sheet Bit Rate 19200 38400 56000 64000 76800 1.All divisors are in hexadecimal. Table 7. Bit Rate Constants, CLK = 30 MHz Bit ...
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Table 8. Bit Rate Constants, CLK = 35 MHz (Sheet Bit Rate 4800 7200 9600 19200 38400 56000 64000 76800 115200 12800 134400 1.All divisors are in hexadecimal. Transmit and receive data can be encoded/decoded in NRZ, ...
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CD2401 — Multi-Protocol Communications Controller Bit rate divisor Figure 11. Data Encoding Figure 12. Transmit Data With External Clock In Note: When using the external receive clock in Receive mode, data is sampled on the low-to-high going edge of RXCIN. ...
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Table 9. Data Clock Selection Using External Clock @ 35 MHz Bit Rate 50 110 150 300 600 1200 2401 3600 4800 7200 9600 19200 38400 56000 64000 76800 115200 128000 1.All divisors are in hexadecimal. 5.6 Hardware Configurations To ...
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CD2401 — Multi-Protocol Communications Controller 5.6.1 Interface to a 32-Bit Data Bus To interface to a 32-bit data bus, two 16-bit data buffers must be used to isolate the CD2401 A/ D[0–15] pins from either half of the 32-bit bus. ...
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CD2401 as a DTE and DCE Interface Table 10 shows the recommended DTE (data terminal equipment) connections between the CD2401 and RS-232C, X.21, and X.21 bis Table 10. DTE Connections CD2401 RXD TXD RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN ...
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CD2401 — Multi-Protocol Communications Controller 6.0 Protocol Processing 6.1 HDLC Processing 6.1.1 Frame Check Sequence FCS is a 16-bit standard computation used in HDLC and defined in ISO 3309. This FCS algorithm is the same used with the synchronous HDLC ...
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If the transmitter is idle in Mark mode, frame transmission is started when data is made available to the transmitter, either by the TDR (Transmit Data register DMA buffer. First, the programmable number of pad characters are transmitted, ...
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CD2401 — Multi-Protocol Communications Controller Indication (0, off) from the remote. If detected, the remainder of the current frame is discarded, and a clear-detect indication is passed to the CPU by the RISR. However, the channel remains in HDLC mode ...
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Receiver In-Band Flow Control The channel can request the remote to stop transmission by sending an XOFF character. Likewise, the channel can request the remote to restart transmission by sending an XON characters. The XON/XOFF characters are transmitted by ...
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CD2401 — Multi-Protocol Communications Controller Table 12. Recommended Signal Connection Mode DCE DTE CTS RTS RTS CTS For example, if the CD2401 is designed to be DCE and automatic out-of-band flow control is desired, connect the DTR pin to the ...
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Table 13. BREAK Sequencing Sequence Send BREAK – Send a line break for at least one 00h–81h character time. Insert delay – To increase the break generation beyond one character time, use the insert delay sequence. The inserted delay is ...
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CD2401 — Multi-Protocol Communications Controller 6.2.6 Special Character Recognition and Range Special character recognition is enabled when the SCDE bit (COR3[4]) is set to ‘1’. The special characters are programmed in the SCHRs, and are the same characters used for ...
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The LNext option (COR7[6]) provides a mechanism to transfer flow control and other special characters, without invoking flow control or special character interrupts at the receiver. If the LNext option is enabled when the LNext character is received, the following ...
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CD2401 — Multi-Protocol Communications Controller Figure 15. CD2401 Async Receive Character Processing CHARACTER RECEIVED N ERROR? Y ISTRIP COR7[7] Y FCErr COR7[5] N LNE COR7[6] Y PREVIOUS CHAR = LNXT N IStrip COR7[7] N SCDE COR3[4] N ESCDE COR3[7] N ...
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Figure 15. CD2401 Async Receive Character Processing (Continued CHAR = BREAK Y Process Break Options IgnBrk NBrkInt DONE Datasheet Multi-Protocol Communications Controller — CD2401 COR6 Action Exception interrupt Discard character Replace with ...
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CD2401 — Multi-Protocol Communications Controller Figure 15. CD2401 Async Receive Character Processing (Continued) B RngDE Y COR3[6] N CR/NL Y OPTIONS COR6[6] N CHAR SCRL Y EXCEPTION CHAR INTERRUPT SCRH N CHAR = DISCARD Y ...
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Bisync Processing In both transmit and receive, the CD2401 interprets the first characters of data to determine the type of frame and compile the corresponding BCC. The host uses COR1 to program parity options and character length, and COR2 ...
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CD2401 — Multi-Protocol Communications Controller Short-Frame Processing Short frames in Bisync mode are generally terminated with minimum two bytes of XOFF. The CD2401 reports these frames as follows: Frame = SYN SYN STX ENQ FF FF Reported as: receive CRC ...
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Data Data SYN CRC At the end of a non-transparent frame: Data Data Data Data Data Data CRC Ends At the end of a transparent frame: Data Data Data Data Data Data CRC Note: For the transparent bisync frames (receive ...
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CD2401 — Multi-Protocol Communications Controller Note:If parity is used, parity is computed/checked on each character, but the LRC of the parity bits is not checked. 6.3.5 Receive State Table Table 16 on page 82 receive microcode character processing, and the ...
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Key: Hunt = Go to SYN Hunt state i = initialize BCC c = calculate CRC 0 = clear state flag, for example 0-RxITB clears the RxITB flag 1 = set state flag Note: When returning to the SYN Hunt ...
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CD2401 — Multi-Protocol Communications Controller Table 18. ETC Byte Sequence This byte must be 80 hex to indicate the start of a Byte 1 command sequence. This byte indicates the required state of the C lead sets the ...
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The SCDE bit enables the detection of the special characters defined in SCHR1–3 the same way as steady-state conditions. When detected for two consecutive character times, a special character detect interrupt is generated and the next repetitions of the same ...
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CD2401 — Multi-Protocol Communications Controller First, the idle character can be supplied as normal data; the drawback is that host intervention is required to either fill the FIFO or supply a new DMA buffer periodically while there is no real ...
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Example 1: (Two SYN mode) Incoming data: Junk Junk SYN SYN Data Data Data Data Data Data Data Data Note: A SYN character detect interrupt is generated after the second SYN. Data is passed to the host: Junk Junk SYN ...
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CD2401 — Multi-Protocol Communications Controller 7.0 Programming Examples This section provides some examples of CD2401 programming. Included are examples of Global and Per-Channel initialization, and two interrupt service routines. The code was written in Borland Turbo C . Figure 16. ...
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Global Initialization The following code segment is an example of global initialization. The host waits for a hardware reset, determined by a non-zero value in the GFRCR. A ‘Reset All’ command is sent to the CD2401 by the CCR. ...
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CD2401 — Multi-Protocol Communications Controller outportb( RBPR, 0x81 ); outportb( TCOR outportb( TBPR, 0x81 ); outportb( CMR, ASYNC ); outportb( COR1, PARIGN | CHAR8 ); outportb( COR2, IXM | TXIBE ); outportb( COR3, STOP1 | FCT ); outportb( ...
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LIVR_GOODDATA: break; case LIVR_EXCEPTION: if( risrl & RISR_EOF ) { { // buffer B next outport( BRBADRU, ib[ch].upper() ); outport( BRBADRL, ib[ch].lower() ); outport( BRBCNT, BUF_MAX ); outport( BRBSTS, 2401_OWN ); ib[ch].nxt_buf(); } ...
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... Reserved – must be written as ‘0’; read back as a ‘don’t care’. Bits 1:0 Channel number 92 Bit 4 Bit 3 Firmware Revision Code Bit 4 Bit 3 Reserved Intel Hex Address: x’82 Motorola Hex Address: x’81 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’EC Motorola Hex Address: x’EE Bit 2 Bit 1 Bit Datasheet ...
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... If these options are changed, an initialization command must be given to the CD2401 through the CCR. chmd2 Datasheet Multi-Protocol Communications Controller — CD2401 C1 C0 Channel Number Bit 4 Bit chmd1 chmd0 Intel Hex Address: x’18 Motorola Hex Address: x’1B Bit 2 Bit 1 Bit 0 chmd2 chmd1 chmd0 Mode HDLC Bisync Async X.21 Reserved Reserved Reserved Reserved 93 ...
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... Bit 4 Bit 3 AdMde0 Flag3 1 byte 2 byte. Flag2 Flag1 Flag0 through Intel Hex Address: x’13 Motorola Hex Address: x’10 Bit 2 Bit 1 Bit 0 Flag2 Flag1 Flag0 Function Minimum of one opening flag, with shared closing/opening flags permitted. Minimum number of opening flags sent. Datasheet ...
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... Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Ignore Chl3 ParM0 0 0 None 0 1 Force (odd parity = force 1, even = force Normal 1 1 Reserved Chl2 Chl1 Chl0 Intel Hex Address: x’13 Motorola Hex Address: x’10 Bit 2 Bit 1 Bit 0 Chl2 Chl1 Chl0 Parity Character Length in Bits ...
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... Bit 6 Bit 5 IXM TxIBE ETC 96 Bit 4 Bit 3 Bit 2 CRCNinv 0 RtsAO Bit 4 Bit 3 Bit 2 0 RLM RtsAO Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 1 Bit 0 CtsAE DsrAE Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 1 Bit 0 CtsAE DsrAE Datasheet ...
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Bit 7 Implied XON Mode IXM has meaning only if TxIBE is set. If transmission stops due to a received XOFF character, then transmission resumes only after the receipt of an XON character or a transmit enable command ...
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... Note: In ASCII mode, data is 7 bits with LRC (odd parity) checking only. In EBCDIC mode, data is 8 bits with CRC checking only. 98 Bit 4 Bit 3 Bit 2 CRCNinv SYN3 SYN2 Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 1 Bit 0 SYN1 SYN0 Datasheet ...
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... This is the count of the number of times the character should be sent. If set to ‘0’, the character is sent continuously until more data is provided to the transmitter (but always a minimum of three times). Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit Section 6.4 on page Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 1 Bit 83). The sequence of bytes 99 ...
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... These bits specify the number of synchronous characters sent. 100 Bit 4 Bit 3 FCS idle pad2 pad1 pad0 Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 pad2 pad1 pad0 Function Reserved 1 pad character sent. 2 pad characters sent. 3 pad characters sent. 4 pad characters sent. Datasheet ...
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... Stop bit length [2:0] These bits specify the length of the Stop bit. Datasheet Multi-Protocol Communications Controller — CD2401 pad2 pad1 pad0 through Bit 4 Bit 3 SCDE Splstp Function Reserved Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 Stop2 Stop1 Stop0 101 ...
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... These bits specify the number of pad characters to be sent when coming out of Idle- In Mark mode. 102 Stop2 Stop1 Stop0 through through Bit 4 Bit 3 FCS idle Stop Bit Length 1 1.5 2 Reserved Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 pad2 pad1 pad0 Datasheet ...
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... RISR. After detection of the special condition, no further data is passed to the host until different data is received. Datasheet Multi-Protocol Communications Controller — CD2401 pad2 pad1 pad0 through Bit 4 Bit 3 SCDE 0 Number of Leading Pads Reserved – do not use. Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 103 ...
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... Note that the maximum value allowable for this field is 12 (0C hex). These 4 bits (binary-encoded field) set the FIFO transfer threshold for both transmit and receive FIFOs, in both Interrupt and DMA Transfer modes. 104 Bit 4 Bit 3 Bit 2 0 FIFO Threshold Intel Hex Address: x’16 Motorola Hex Address: x’15 Bit 1 Bit 0 Datasheet ...
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... DTR* pin deasserts. When the number of characters is equal to or less than the threshold, DTR* is asserted. Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit Flow Control Threshold Intel Hex Address: x’17 Motorola Hex Address: x’14 Bit 1 Bit 0 105 ...
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... CR discarded and NL translated to CR discarded discarded and NL translated to CR. IgnBrk NBrkInt 0 0 Generate an exception interrupt Translate to a NULL character Reserved 1 1 Discard character. Intel Hex Address: x’1B Motorola Hex Address: x’18 Bit 2 Bit 1 Bit 0 ParMrk INPCK ParInt Function Function Datasheet ...
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... Translate to a sequence of FF NULL and the error character, pass on as Good Data Reserved Reserved by FF hex to distinguish it from a parity error sequence. Bit 4 Bit 3 Special Frame Termination Character Function Intel Hex Address: x’1B Motorola Hex Address: x’18 Bit 2 Bit 1 Bit 0 107 ...
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... LNext character is not processed for special character matching or flow control. 108 Bit 4 Bit 3 Bit 2 SYN Character Bit 4 Bit 3 Bit Intel Hex Address: x’1B Motorola Hex Address: x’18 Bit 1 Bit 0 Intel Hex Address: x’04 Motorola Hex Address: x’07 Bit 1 Bit 0 ONLCR OCRNL Datasheet ...
Page 109
... Datasheet Multi-Protocol Communications Controller — CD2401 OCRNL special action translated to NL translated to the sequence CR NL. CR translated to NL, and NL translated to the sequence NL. Bit 4 Bit 3 User-Defined Special Character XON Character Function Intel Hex Address: x’1C Motorola Hex Address: x’1F Bit 2 Bit 1 Bit 0 109 ...
Page 110
... Bit 2 User-Defined Special Character Bit 4 Bit 3 Bit 2 User-Defined Special Character Intel Hex Address: x’1D Motorola Hex Address: x’1E Bit 1 Bit 0 Intel Hex Address: x’1E Motorola Hex Address: x’1D Bit 1 Bit 0 Intel Hex Address: x’1F Motorola Hex Address: x’1C Bit 1 Bit 0 Datasheet ...
Page 111
... Bit 3 Bit 4 Bit 3 User-Defined Literal Next Character Intel Hex Address: x’20 Motorola Hex Address: x’23 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’21 Motorola Hex Address: x’22 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’2D Motorola Hex Address: x’2E Bit 2 Bit 1 Bit 0 111 ...
Page 112
... Intel Hex Address: x’1C Motorola Hex Address: x’1F Bit 1 Bit 0 Intel Hex Address: x’1D Motorola Hex Address: x’1E Bit 1 Bit 0 Intel Hex Address: x’1E Motorola Hex Address: x’1D Bit 1 Bit 0 Intel Hex Address: x’1F Motorola Hex Address: x’1C Bit 1 Bit 0 Datasheet ...
Page 113
... Multi-Protocol Communications Controller — CD2401 page 94 Bit 4 Bit 3 Bit Bit 4 Bit 3 Bit 2 Receive Bit Rate Period (Divisor) through page 108). Intel Hex Address: x’D4 Motorola Hex Address: x’D6 Bit 1 Bit Poly Intel Hex Address: x’C9 Motorola Hex Address: x’CB Bit 1 Bit 0 113 ...
Page 114
... Encoding 0 0 NRZ 0 1 NRZI 1 0 Manchester 1 1 Reserved clkSel2 clkSel1 clkSel0 Section 5.5 on page Intel Hex Address: x’CA Motorola Hex Address: x’C8 Bit 2 Bit 1 Bit 0 ClkSel2 ClkSel1 ClkSel0 Clock Source Clk 0 Clk 1 Clk 2 Clk 3 Clk 4 Reserved External clock Reserved 58. Datasheet ...
Page 115
... Section 5.5 on page Intel Hex Address: x’C1 Motorola Hex Address: x’C3 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’C2 Motorola Hex Address: x’C0 Bit 2 Bit 1 Bit 0 0 LLM 0 Clock Source 0 Clk 0 1 Clk 1 0 Clk 2 1 Clk 3 0 Clk 4 1 Reserved 0 External clock ...
Page 116
... All other combinations are legal, and the order of processing is: 1. Clear channel 2. Initialize channel 3. Enable receive 4. Disable receive 5. Enable transmit 6. Disable transmit 116 Bit 4 Bit 3 Bit 2 RstAll EnTx DisTx Intel Hex Address: x’10 Motorola Hex Address: x’13 Bit 1 Bit 0 EnRx DisRx Datasheet ...
Page 117
Note: Processing CCR commands is a low-priority task for the internal firmware, since they seldom occur. The user must take care when waiting for command completions at critical times, that is, during interrupt service routines. Bit 7 For mode 1, ...
Page 118
... For Synchronous modes, this command puts the receiver back into SYN/Flag Hunt mode. Note: This command is not available in revisions prior to Revision ‘H’. Bits 3:0 Reserved – must be ‘0’. 118 Bit 4 Bit 3 Bit ClrRcv Intel Hex Address: x’10 Motorola Hex Address: x’13 Bit 1 Bit Datasheet ...
Page 119
... Bit 4 Bit 3 0 SndSpc SSPC2 SSCP1 SSPC0 Intel Hex Address: x’11 Motorola Hex Address: x’12 Bit 2 Bit 1 Bit 0 SSPC2 SSPC1 SSPC0 Function 0 Reserved 1 Send special character 1 0 Send special character 2 1 Send special character 3 0 Send special character 4 1 Reserved 0 Reserved ...
Page 120
... Asynchronous Mode If the host determines that a flow control state is inappropriate, it can be cleared by enabling/ disabling the transmitter or receiver by a CCR command. 120 Bit 4 Bit 3 Bit 2 RxMark TxEn TxFlag Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 1 Bit 0 TxFrame TxMark Datasheet ...
Page 121
... Bit 0 Reserved – always returns ‘0’ when read. Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 0 TxEn TxFloff Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 1 Bit 0 TxFlon 0 121 ...
Page 122
... Bit 4 Bit 3 Bit 2 0 TxEn TxITB Table 16 on page 82). Bit 4 Bit 3 Bit 2 0 TxEn 0 Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 1 Bit 0 TxFrame 0 Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 1 Bit 0 TxSpc 0 Datasheet ...
Page 123
... Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 DTRop 0 0 Bit 4 Bit 3 Bit 2 DTRop 0 0 Intel Hex Address: x’DC Motorola Hex Address: x’DE Bit 1 Bit 0 DTR RTS Intel Hex Address: x’DD Motorola Hex Address: x’DF Bit 1 Bit 0 DTR RTS 123 ...
Page 124
... Bits 7:2 User-defined. These six bits can be used as the CD2401 device ID number. Bits 1:0 Interrupt Type [1:0] These two bits indicate the group/type of interrupt occurring. 124 Bit 4 Bit 3 Bit Intel Hex Address: x’0A Motorola Hex Address: x’09 Bit 1 Bit 0 IT1 IT0 Datasheet ...
Page 125
... IT0 0 1 Group 1: modem signal change interrupt/general timer interrupt Group 2: transmit data interrupt Group 3: receive data interrupt Group 3: receive exception interrupt. Bit 4 Bit 3 0 RxD Group/Type Intel Hex Address: x’12 Motorola Hex Address: x’11 Bit 2 Bit 1 Bit 0 TIMER TxMpty TxD 125 ...
Page 126
... These bits provide the currently active interrupt level. 126 Bit 4 Bit Channel Number Bit 4 Bit TLvl [0] Intel Hex Address: x’25 Motorola Hex Address: x’26 Bit 2 Bit 1 Bit Channel 0 Channel 1 Channel 2 Channel 3 Intel Hex Address: x’E0 Motorola Hex Address: x’E2 Bit 2 Bit 1 Bit 0 MLvl [0] CLvl [0] Datasheet ...
Page 127
... Currently in a transmit interrupt service, TIR provides the 1 0 current channel number. Currently in a receive interrupt service, RIR provides the 1 1 current channel number. Bit 4 Bit 3 User-Assigned Priority Match Value Function Intel Hex Address: x’E3 Motorola Hex Address: x’E1 Bit 2 Bit 1 Bit 0 127 ...
Page 128
... Bit 3 0 Rvct [1] Ren Ract Reoi Intel Hex Address: x’EF Motorola Hex Address: x’ED Bit 2 Bit 1 Bit 0 Rvct [0] Rcn [1] Rcn [0] Sequence of Events Idle Receive interrupt requested, but not asserted. Receive interrupt is asserted. Receive interrupt is acknowledged. Receive interrupt service routine is complete. Datasheet ...
Page 129
... This bit indicates an X.21 data transfer phase clear signal has been detected. This is Datasheet Multi-Protocol Communications Controller — CD2401 RISR high RISR low Bit 4 Bit 3 Bit 2 CRC OE Reslnd Intel Hex Address: x’8A Motorola Hex Address: x’ Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 1 Bit 0 0 ClrDct 129 ...
Page 130
... Special character 4 matched (only if COR3[ enabled). Character is within the inclusive range of the characters in the SCRs (only if COR3[6] is enabled Special character match can be enabled for error characters by COR7. Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 2 Bit 1 Bit Break Status Datasheet ...
Page 131
... Lead Value 0 = OFF Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 CRC OE 0 Bit 4 Bit 3 Bit 2 SCdet0 OE PE Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 1 Bit Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 1 Bit 0 0 LChg 131 ...
Page 132
... Matched the value in SCHR1. 0 Matched the value in SCHR2. 1 Matched the value in SCHR3. 0 All ‘0’ condition. 1 All ‘1’ condition. 0 Alternating ‘0’ and ‘1’ condition. 1 SYN detect. Intel Hex Address: x’8B Motorola Hex Address: x’88 Bit 2 Bit 1 Bit Datasheet ...
Page 133
... Bit 7 Bit 6 Bit Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 RxCt4 RxCt3 RxCt2 Bit 4 Bit 3 Bit Intel Hex Address: x’33 Motorola Hex Address: x’30 Bit 1 Bit 0 RxCt1 RxCt0 Intel Hex Address: x’F8 Motorola Hex Address: x’F8 Bit 1 Bit 133 ...
Page 134
... Bit 3 No Transfer of Data If no data is transferred from the receive FIFO during a receive interrupt, this bit must be set by the host. 134 Bit 4 Bit 3 Bit 2 SetTm1 NoTrans Gap2 Intel Hex Address: x’87 Motorola Hex Address: x’84 Bit 1 Bit 0 Gap1 Gap0 Datasheet ...
Page 135
... Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 User-Assigned Priority Match Value Bit 4 Bit 3 Bit 2 0 Tvct [1] Tvct [0] Intel Hex Address: x’E2 Motorola Hex Address: x’E0 Bit 1 Bit 0 Intel Hex Address: x’EE Motorola Hex Address: x’EC Bit 1 Bit 0 Tcn [1] Tcn [0] 135 ...
Page 136
... Tact Teoi Idle Transmit interrupt requested, but not asserted Transmit interrupt is asserted Transmit interrupt is acknowledged Transmit interrupt service routine is complete. Bit 4 Bit 3 UE BA/BB Sequence of Events Intel Hex Address: x’89 Motorola Hex Address: x’8A Bit 2 Bit 1 Bit 0 0 TxEmpty TxDat Datasheet ...
Page 137
... Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 TxCt4 TxCt3 TxCt2 Bit 4 Bit 3 Bit Section 7.4 on page Intel Hex Address: x’83 Motorola Hex Address: x’80 Bit 1 Bit 0 TxCt1 TxCt0 Intel Hex Address: x’F8 Motorola Hex Address: x’F8 Bit 1 Bit 90. If the BYTESWAP pin is 137 ...
Page 138
... No Transfer of data If no data is transferred to the transmit FIFO during a data transfer interrupt, this bit must be set by the host. Bits 2:0 Reserved – must be zero. 138 Bit 4 Bit 3 Bit 2 SetTm1 Notrans 0 Intel Hex Address: x’86 Motorola Hex Address: x’85 Bit 1 Bit Datasheet ...
Page 139
... Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 User-Assigned Priority Match Value Bit 4 Bit 3 Bit 2 0 Mvct 1 Mvct 0 Intel Hex Address: x’E1 Motorola Hex Address: x’E3 Bit 1 Bit 0 Intel Hex Address: x’ED Motorola Hex Address: x’EF Bit 1 Bit 0 Mcn 1 Mcn 0 139 ...
Page 140
... Men Mact Meo Idle Modem interrupt requested, but not asserted Modem interrupt is asserted Modem interrupt is acknowledged Modem interrupt service routine is complete. Bit 4 Bit Sequence of Events Intel Hex Address: x’88 Motorola Hex Address: x’8B Bit 2 Bit 1 Bit 0 0 Timer2 Timer1 Datasheet ...
Page 141
... This register is write only. No misoperation occurs if the register is read, but the read value is not consistent. Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 SetTm1 0 0 Bit 4 Bit 3 Bit 2 0 ByteDMA 0 Intel Hex Address: x’85 Motorola Hex Address: x’86 Bit 1 Bit Intel Hex Address: x’F4 Motorola Hex Address: x’F6 Bit 1 Bit 141 ...
Page 142
... This status bit is used internally to manage data alignment in the transmit FIFO. 142 Bit 4 Bit 3 Bit 2 Binary Value Bit 4 Bit 3 Bit 2 Append Ntbuf Tbusy Intel Hex Address: x’8D Motorola Hex Address: x’8E Bit 1 Bit 0 Intel Hex Address: x’1A Motorola Hex Address: x’19 Bit 1 Bit 0 Nrbuf Rbusy Datasheet ...
Page 143
... Bit 6 Bit 5 Datasheet Multi-Protocol Communications Controller — CD2401 Bit 12 Bit 11 Binary Address Value, 32-bit Address bits 15:8 Bit 4 Bit 3 Binary Address Value, 32-bit Address bits 7:0 Intel Hex Address: x’40 Motorola Hex Address: x’42 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 143 ...
Page 144
... Binary Address Value, 32-bit Address, bits 15:8 Bit 4 Bit 3 Binary Address Value, 32-bit Address, bits 7:0 Intel Hex Address: x’42 Motorola Hex Address: x’40 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’44 Motorola Hex Address: x’46 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 145
... Binary Count Value, 16-bit Count bits 15:8 Bit 4 Bit 3 Binary Count Value, 16-bit Count bits 7:0 Intel Hex Address: x’46 Motorola Hex Address: x’44 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’48 Motorola Hex Address: x’4A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 145 ...
Page 146
... Bit 4 Bit Intel Hex Address: x’4A Motorola Hex Address: x’48 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’4C Motorola Hex Address: x’4F Bit 2 Bit 1 Bit 2401own Intel Hex Address: x’4D Motorola Hex Address: x’4E Bit 2 Bit 1 Bit 2401own Datasheet ...
Page 147
... Binary Address Value, 32-bit Address bits 31:24 Bit 4 Bit 3 Binary Address Value, 32-bit Address bits 23:16 Intel Hex Address: x’3C Motorola Hex Address: x’3E Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’3E Motorola Hex Address: x’3C Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 147 ...
Page 148
... Binary Address Value, 32-bit Address bits 31:24 134) for the insertion of status Intel Hex Address: x’50 Motorola Hex Address: x’52 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’52 Motorola Hex Address: x’50 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 149
... Binary Address Value, 32-bit Address bits 23:16 Bit 4 Bit 3 Binary Address Value, 32-bit Address bits 31:24 Intel Hex Address: x’54 Motorola Hex Address: x’56 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’56 Motorola Hex Address: x’54 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 149 ...
Page 150
... Intel Hex Address: x’58 Motorola Hex Address: x’5A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’5A Motorola Hex Address: x’58 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’5C Motorola Hex Address: x’5F Bit 2 Bit 1 Bit 0 0 INTR 2401own Datasheet ...
Page 151
... ATADR and ATCNT as normal, but when new data is appended to the buffer, the A/ BTBCNT can be updated. When the A buffer is used in Append mode, the CD2401 does not set the Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 UE Append 0 Intel Hex Address: x’5D Motorola Hex Address: x’5E Bit 1 Bit 0 INTR 2401own 151 ...
Page 152
... Binary Address Value, 32-bit Address bits 31:24 Bit 4 Bit 3 Binary Address Value, 32-bit Address bits 23:16 Intel Hex Address: x’38 Motorola Hex Address: x’3A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’3A Motorola Hex Address: x’38 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 153
... Binary Value bits 7:0 Bit 4 Bit 3 Bit 2 Binary Value Intel Hex Address: x’D8 Motorola Hex Address: x’DA Bit 1 Bit 0 Intel Hex Address: x’26 Motorola Hex Address: x’24 Bit 9 Bit 8 Bit 1 Bit 0 Intel Hex Address: x’26 Motorola Hex Address: x’25 Bit 1 Bit 0 153 ...
Page 154
... Binary Value Intel Hex Address: x’27 Motorola Hex Address: x’24 Bit 2 Bit 1 TxFloff TxFlon Intel Hex Address: x’28 Motorola Hex Address: x’2A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’28 Motorola Hex Address: x’2B Bit 2 Bit 1 Bit 0 Datasheet Bit 0 0 ...
Page 155
... In a single-interrupt routine, only one general timer can be restarted this way. Datasheet Multi-Protocol Communications Controller — CD2401 Bit 12 Bit 11 Bit 10 Binary Value Bit 4 Bit 3 Bit 2 Binary Value Intel Hex Address: x’29 Motorola Hex Address: x’2A Bit 9 Bit 8 Intel Hex Address: x’2A Motorola Hex Address: x’29 Bit 1 Bit 0 155 ...
Page 156
... This Asynchronous mode timer is managed by the CD2401 to implement embedded transmit delays when that option is used by the host (see description of COR2). This register should not be modified by the host under any circumstances. 156 Bit 4 Bit 3 Bit 2 Binary Value Intel Hex Address: x’2A Motorola Hex Address: x’29 Bit 1 Bit 0 Datasheet ...
Page 157
Electrical Specifications Note: Verify with your local sales office that you have the latest datasheet before finalizing a design. 9.1 Absolute Maximum Ratings Operating ambient temperature (T Storage temperature 150 C All voltages with respect to ...
Page 158
CD2401 — Multi-Protocol Communications Controller 9.3 AC Electrical Characteristics Symbol t Period of CLK input (35 MHz maximum) PERIOD t CLK high to BUSCLK high 1 t CLK high to BUSCLK low 2 Bus Arbitration t CLK high to BGACK* ...
Page 159
Symbol t R/W* setup to CLK high 44 t CLK high to data valid 45 t Data setup time to CLK high 46 t Data hold time after CLK high 47 t Address setup time to CLK high 48 t ...
Page 160
CD2401 — Multi-Protocol Communications Controller Figure 18. Slave Read Cycle Timing CLK BUSCLK t 41 DS A[7:0] A/D[15:0] DTACK DATEN* /DATDIR* 160 ...
Page 161
Figure 19. Slave Write Cycle Timing CLK BUSCLK t 41 DS A[7:0] A/D[15:0] DTACK DATEN* Datasheet Multi-Protocol Communications Controller — CD2401 ...
Page 162
CD2401 — Multi-Protocol Communications Controller Figure 20. Interrupt Acknowledge Cycle Timing CLK BUSCLK t 61 DS A[7:0] A/D[15:0] DTACK DATEN*/DATDIR* 162 ...
Page 163
Figure 21. Bus Arbitration Cycle Timing CLK BUSCLK BR* BGIN* ADLD* A[7:0] A/D[15:0] AS* AEN*/DATEN*/ DATDIR* BGACK* R/W* NOTE: In DMA Read cycle, these pins will be tristate; in DMA Write cycle, these pins will be D[15:0]. Datasheet Multi-Protocol Communications ...
Page 164
CD2401 — Multi-Protocol Communications Controller Figure 22. Bus Release Timing CLK BUSCLK AS*, DS* A[7:0] A/D[15:0] BGACK* R/W* AEN*/DATEN*/ DATDIR* 164 Datasheet ...
Page 165
Figure 23. DMA Read Cycle Timing CLK BUSCLK A[7:0] A/D[15:0] DTACK* BERR* Datasheet Multi-Protocol Communications Controller — CD2401 ...
Page 166
CD2401 — Multi-Protocol Communications Controller Figure 24. DMA Write Cycle Timing CLK BUSCLK t 24 AS* DS A[7: A/D[15:0] DTACK* BERR* 166 BERR* Timing setup ...
Page 167
... Revision I or older are available in the EIAJ package; Revision M and newer are available in the JEDEC package. 2. Dimensions are in millimeters (inches), and controlling dimension is millimeter. 3. Before beginning any new design with this device, please contact Intel for the latest package information. Datasheet Multi-Protocol Communications Controller — CD2401 22 ...
Page 168
... CD2401 — Multi-Protocol Communications Controller 11.0 Ordering Information Example Communications, Data † Contact Intel Corporation for up-to-date information on revisions. 168 SCD240110QCM Product line: Part number Internal reference number † Revision Temperature range Commercial Package type: MQFP (metric quad flat pack) Datasheet ...
Page 169
Index A abbreviations 13 absolute maximum ratings 157 AC electrical characteristics bus arbitration 158 DMA read 158 DMA write 158 host read/write 158 interrupt acknowledge 159 acronyms 14 Addressing mode 94 Append mode 56 Async-HDLC/PPP mode 31, 102, 119, 122, ...
Page 170
High-Impedance mode 19 host interface 35 host read and write cycles 35 host read/write 158 I Idle in Mark mode 100 Idle mode 100 interrupt acknowledge 159 interrupts acknowledge cycle 39 contexts and channels 38 groups and types 39 IACK ...
Page 171
R read cycle, host 36 receive buffer interrupts 56 receive bus errors 57 receive DMA transfer 51 receive FIFO operation 43 receive timeout 57 Receive Transfer mode 93 receiver A and B buffers 51 register definitions 26 register table 21 ...
Page 172
REOIR 23, 31, 134 RFOC 23, 31, 133 RIR 23, 30, 128 RISR 23, 31, 129 RISRh 23, 31, 132 RISRl 23, 31, 129 RPILR 23, 30, 127 Timer registers GT1 26, 34, 154 GT1h 26, 34, 155 GT1l 26, ...
Page 173
Bit Index 146 150 2401own , A 119 AbortTx 94 AdMde[1:0] 94 AFLO 100 Alt1 119 AppdCmp 142 150 Append , B 132 136 BA/ BCC 132 136 146 150 Berr , , , 143 147 152 Binary ...
Page 174
InitCh 106 INLCF 106 INPCK 150 INTR 108 IStrip 124 IT[1:0] 96 IXM L 131 LChg 115 LLM 108 LNE 98 LRC 131 LVal M 139 Mact 139 Mcn[1:0] 125 Mdm 139 Men 139 Meo 126 MLvl[1:0] 139 Mvct[1:0] ...
Page 175
Tvct[1:0] 137 TxCt[4:0] 125 TxD 136 TxDat 136 TxEmpty 120 121 122 154 TxEn , , , 120 TxFlag 121 154 TxFloff , 121 154 TxFlon , 120 122 TxFrame , 96 TxIBE 122 TxITB 120 TxMark 93 TxMode ...
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