SCD240110QCM Intel, SCD240110QCM Datasheet - Page 145
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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8.6.4.4
8.6.4.5
Datasheet
Register Name: BRBADRU
Register Description: Receive Buffer ‘B’ 32-bit Address – upper word
Default Value: x’0000
Access: Word Read/Write
Register Name: ARBCNT
Register Description: Receive Buffer A Byte Count
Default Value: x’0000
Access: Word Read/Write
Bit 15
Bit 15
Bit 7
Bit 7
B Receive Buffer Address – Upper (BRBADRU) Register
This register contains the start addresses of the B external buffer used by the CD2401 to store the
receive data block. This register is written to by the host and copied internally to control the data
transfer to the memory.
A Buffer Receive Byte Count (ARBCNT) Register
Bit 14
Bit 14
Bit 6
Bit 6
Bit 13
Bit 13
Bit 5
Bit 5
Binary Address Value, 32-bit Address, bits 23:16
Binary Address Value, 32-bit Address, bits 31:24
Binary Count Value, 16-bit Count bits 15:8
Binary Count Value, 16-bit Count bits 7:0
Bit 12
Bit 12
Bit 4
Bit 4
Multi-Protocol Communications Controller — CD2401
Bit 11
Bit 11
Bit 3
Bit 3
Bit 10
Bit 10
Bit 2
Bit 2
Motorola Hex Address: x’4A
Motorola Hex Address: x’44
Bit 9
Bit 1
Bit 9
Bit 1
Intel Hex Address: x’46
Intel Hex Address: x’48
Bit 8
Bit 0
Bit 8
Bit 0
145
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