SCD240110QCM Intel, SCD240110QCM Datasheet - Page 90

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
7.3
7.4
90
HDLC DMA Channel Setup Example
This per-channel initialization code example is for the HDLC protocol at 38.4 kbps with NRZI
encoding. The setup specifies two extra opening flags before frames, no address matching, and that
DMA transfers should be used.
Receive DMA Interrupt Service Routine
The following code example shows an interrupt service routine for the CD2401 in DMA mode.
The buffer class array ‘ib[ ]’ is used for notational convenience, and its exact implementation is
user-defined. The upper ( ) and lower ( ) functions should return the upper and lower 16 bits of the
DMA address for the current buffer segment. The ‘nxt_buf( )’ accesses the next segment.
If the system uses separate interrupt handlers for receive, transmit, and modem interrupts, the
channel number can be obtained from the lower two bits of the Interrupt register (RIR, TIR, or
MIR). Otherwise, first use LIVR to determine the type of interrupt. Receive ‘Good Data’ interrupts
should not occur during DMA transfers. The normal exception is when an end-of-frame is
received.
The DMABSTS register shows which buffer the CD2401 expects to use next. Fill the descriptor
registers for that buffer, including the 2401own bit and return. The last access to the CD2401
during the service routine is the REOIR.
int risrl = inportb( RISRL );
int ch = inportb( RIR ) & 0x03;
outportb( RBPR, 0x81 );
outportb( TCOR, 0 );
outportb( TBPR, 0x81 );
outportb( CMR, ASYNC );
outportb( COR1, PARIGN | CHAR8 );
outportb( COR2, IXM | TXIBE );
outportb( COR3, STOP1 | FCT );
outportb( COR4, thresh );
outportb( COR5, 0 );
outportb( LIVR, 0x30 );
outportb( RCOR, DPLL_NRZI );
outportb( RBPR, 64 );
outportb( TCOR, 0 );
outportb( TBPR, 64 );
outportb( CMR, RX_DMA | TX_DMA | HDLC ); // Mode register
outportb( CPSR, CPSR_CRC_V41 );
outportb( COR1, NO_ADDR | FLAG_2 );
outportb( COR2, CRC_V41 );
outportb( COR3, 0 );
outportb( COR4, thresh );
outportb( COR5, 0);
// Baud Rate divisor
// Transmit clock option
// Baud Rate divisor
// Async Mode, interrupt
// 8 bit chars, no parity
// in-band flow,implied XON
// 1 stop, flow control
// FIFO threshold
// Set interrupt vector
// Receive clock option
// Baud rate divisor
// Transmit clock option
// Baud rate divisor
// CRC polynomial select
// No address matching,
// 2 opening flags
// FIFO threshold
// low status
// channel number
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