SCD240110QCM Intel, SCD240110QCM Datasheet - Page 20
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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CD2401 — Multi-Protocol Communications Controller
20
BYTESWAP
Table 1.
Symbol
GND
V
DD
Pin Descriptions (Sheet 4 of 4)
2, 20, 62, 70,
8, 45, 79, 96
Number
82, 99
Pin
31
Type
–
–
I
BYTESWAP: This pin alters the byte ordering of data during certain 16-bit
transfers and changes the half of the data bus on which byte transfers are made
to comply with Intel or Motorola processor systems. BYTESWAP does not
alter the bus handshake signals. When the BYTESWAP pin is high, the byte of
A/D[7:0] precedes that of A/D[15:8] in a string of transmit or receive bytes; when
BYTESWAP is low, A/D[15:8] precedes A/D[7:0].
When the BYTESWAP pin is high, bytes are transferred on A/D[7:0] when A[0]
is low, and on A/D[15:8] when A[0] is high. When BYTESWAP is low, bytes are
transferred on A/D[15:8] when A[0] is low, and A/D[7:0] when A[0] is high. A
different register map is used, depending on the state of this pin.
POWER
GROUND
BYTESWAP
0
1
Description
Byte Alignment
Motorola
Intel
Datasheet
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