SCD240110QCM Intel, SCD240110QCM Datasheet - Page 93
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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8.2
8.2.1
Datasheet
Register Name: CMR
Register Description: Channel Mode
Default Value: x’02
Access: Byte Read/Write
RxMode
Bit 7
Option Registers
Channel Mode Register (CMR)
Bit 7
Bit 6
Bits 5:3
Bits 2:0
TxMode
Bit 6
Receive Transfer Mode
0 = Interrupt
1 = DMA
Transmit Transfer Mode
0 = Interrupt
1 = DMA
Reserved – must be ‘0’.
Protocol mode select [2:0]
If these options are changed, an initialization command must be given to the CD2401
through the CCR.
Bit 5
chmd2
0
C1
0
0
1
1
0
0
0
0
1
1
1
1
C0
0
1
0
1
Bit 4
chmd1
0
0
0
1
1
0
0
1
1
Multi-Protocol Communications Controller — CD2401
Channel Number
chmd0
Bit 3
0
1
0
1
0
1
0
1
0
0
1
2
3
HDLC
Bisync
Async
X.21
Reserved
Reserved
Reserved
Reserved
chmd2
Bit 2
Mode
Motorola Hex Address: x’1B
chmd1
Bit 1
Intel Hex Address: x’18
chmd0
Bit 0
93
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