SCD240110QCM Intel, SCD240110QCM Datasheet - Page 102
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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CD2401 — Multi-Protocol Communications Controller
102
Register Name: COR3
Register Description: Channel Option 3
Default Value: x’00
Access: Byte Read/Write
Sndpad
Bit 7
COR3 — Bisync Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
Bit 6
S55
Send Pad character
0 = CD2401 does not send any pad characters.
1 = CD2401 sends pad characters before sending SYN when coming out of the Idle-
In Mark mode.
Send pad pattern
0 = hex AA is sent as pad character.
1 = hex 55 is sent as pad character.
FCS Preset
0 = FCS is preset to all ‘0’s.
1 = FCS is preset to all ‘1’s.
FCS mode
0 = normal FCS mode. The CD2401 generates and appends CRC on transmit and
validates CRC on receiving, using the CRC polynomial selected through CPSR.
1 = disable FCS generation and checking. The CD2401 treats the entire frame as
data.
Idle mode
0 = idle in SYN.
1 = idle in mark.
Pad count [2:0] – transmit frame leading pads
These bits specify the number of pad characters to be sent when coming out of Idle-
In Mark mode.
FCSPre
Bit 5
Stop2
0
0
1
0
0
1
1
Bit 4
FCS
through
through
Stop1
1
1
0
0
0
1
1
Bit 3
idle
Stop0
0
1
0
0
1
0
1
pad2
Bit 2
Stop Bit Length
Motorola Hex Address: x’16
Reserved
pad1
Bit 1
1.5
1
2
Intel Hex Address: x’15
Datasheet
pad0
Bit 0
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