CXA2095 Sony Corporation, CXA2095 Datasheet
CXA2095
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CXA2095 Summary of contents
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... Y/C/RGB/Sync/Deflection for Color TV Description The CXA2095S is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for NTSC system color TVs onto a single chip. The following functions have been added to the same function IC, CXA2025S ...
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... CC – 2 – CXA2095S CC ...
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... Provide a bias of about V signal (including sync, 100% white, 2Vp-p CV 30k signal) with a 570mVp-p burst level. 35µ Power supply for the video block 50µ 10k – 3 – Description /2 and input bus protocol SCL (Serial Clock) input. VILMAX = 1.5V VIHMIN = 3.5V CXA2095S ...
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... Y) signal via a capacitor. The signal is clamped to 6.2V at the burst timing of the signal input to the sync input (Pin 44). GND for the video block switch control input. 100µ When YM is high, the Y/C block signal is attenuated by 6dB. 147 VILMAX = 0.4V VIHMIN = 1.0V 40k VIHMAX = 3.0V – 4 – CXA2095S Description ...
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... ABL control signal input and VSAW high voltage SV CC fluctuation compensation signal input. High voltage compensation has linear control characteristics for the pin voltage range of about 147 8V to 1V. ABL operates when the pin voltage becomes lower than about 1.2V. – 5 – CXA2095S Description For the CXA2025S, the loop ...
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... VDRIVE–. The Vprotect function can 30k also be operated by this pin. 24k 400µ 1.4k 25µ V parabola wave output. 15k 78k 800µ Sample-and-hold for AGC which maintains the V 1.2k sawtooth wave at a constant amplitude. Connect to GND via a capacitor. – 6 – CXA2095S Description 2 C bus. ...
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... JV CC 1.2k 46k CR connection for the AFC lag-lead filter. 50µ 50µ 10k Connect the 32f 400µ 50µ GND for the deflection block. – 7 – CXA2095S Description 2 C bus. VCO ceramic oscillator. H ...
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... Burst gate pulse output. This pulse positive polarity pulse. While this pulse is gated near V-Sync for the CXA2025S constantly output for the 15k CXA2095S. 1k – 8 – CXA2095S Description control. 0 ...
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... Pin Symbol Equivalent circuit No. 47 FSCOUT 147 Sub carrier output. Output level: 5.9VDC, 0.5Vp-p 300µ This pin is not connected. Connect to GND normally to prevent interference to others. – 9 – CXA2095S Description ...
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... CXA2095S ...
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... CXA2095S ...
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... CXA2095S ...
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... CXA2095S ...
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... Hex SUB-COLOR = 7 Hex SUB-BRIGHT = 1F Hex G-DRIVE = 2A Hex AGING2 = 0 G-CUTOFF = 0 Hex EY- RON = 1 BON = 1 VOFF = 0 CD-MODE = 0 V-SIZE = 1F Hex V-POSITION = 1F Hex S-CORR = 0 Hex H-SIZE = 1F Hex PIN-COMP = 1F Hex H-POSITION = 7 Hex UP-CPIN = 0 Hex AFC-BOW = 7 Hex V-ASPECT = 0 Hex HBLKSW = 0 JMPSW = 0 LO-VLIN = 0 Hex RIGHT-BLK = 7 Hex – 14 – CXA2095S ...
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... CXA2095S ...
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... Electrical Characteristics Measurement Circuit Signal sources are all GND unless otherwise specified in the Measurement conditions column of Electrical Characteristics. ABL is 9V unless otherwise specified. – 16 – CXA2095S ...
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... DC-TRAN TOT D-COL PRE-OVER SHP-F0 CTRAP-ADJ SUB-HUE GAMMA AGING1 AGING2 EY-SW CD-MODE2 B-CUTOFF VOFF FHHI AKBOFF CD-MODE V-COMP AFC-MODE V-LIN REF-POSI VBLKW PIN-PHASE LO-CPIN AFC-ANGLE ZOOMSW HBLKSW JMPSW LO-VLIN RIGHT-BLK : Don't care BIT3 BIT2 BIT1 0 1 CXA2095S BIT0 VM D-PIC AXIS ABL 0 BIT0 0 ...
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... R-Y, G-Y axis selector switch 0 = Japan axis R-Y: 95° axis RGB output: 2.4Vp-p (I/O gain: +4.7dB, 1.4Vp-p input) Flesh color appears red. Flesh color appears green. Point of inflection: 30 IRE B output: 1.1Vp-p (I/O gain: +5.7dB, 0.57Vp-p input) 0.60, G-Y: 236° 0.33 R-Y: 105° 0.78, G-Y: 236° 0.33 (B-Y: 0° 1) – 18 – CXA2095S ...
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... CTRAP-ADJ (4) : Chroma trap f0 adjustment (Y block chroma trap current control +300kHz 7H = 0kHz FH = –300kHz fsc adjustable to –30dB or less (SHP-F0 min.); adjustment value SUB-COLOR (4) : Color gain control (ACC reference level control –4.0dB 7H = 0dB FH = +2.1dB –300mV from REF-P level (PRE:OVER) – 19 – CXA2095S ...
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... B-Y axis adjustable to 0° –300mV from REF-P level –3.8dB 0dB +2.5dB 60 IRE flat signal output from Y block when input is no signal Black level output –3.8dB 0dB +2.5dB selected when Pin 9 is high.) selected when Pin 9 is high.) – 20 – CXA2095S ...
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... IKIN pin input is assumed 100%) (B/R: Bch reference pulse amplitude when Rch reference pulse amplitude of IKIN pin input is assumed 100%) vary according to V-POSITION.) automatically selected (V oscillator frequency is 55Hz during no signal mode (free run).) – 21 – CXA2095S AFC normal mode Oscillator frequency fixed to maximum value (16.252kHz). ...
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... Picture position drops, VDRIVE+ output DC Down Center DC: 3V Picture position rises, VDRIVE+ output DC Up compressed. picture expanded. Horizontal picture size decreases, EWDRIVE output DC Down. Amplitude: 0.58Vp-p, center DC: 4V (when V-ASPECT = 2FH) Horizontal picture size increases, EWDRIVE output DC Up – 22 – CXA2095S ...
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... Horizontal size for top of picture decreases. (0.7Vp-p, 4:3 mode) Horizontal size for top of picture increases. Horizontal size for bottom of picture decreases. (0.7Vp-p, 4:3 mode) Horizontal size for bottom of picture increases. respect to picture center respect to picture center 16:9 CRT full 4:3 CRT full (amplitude: 1.23Vp-p) – 23 – CXA2095S ...
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... Blanking for the bottom of the picture starts 251H after VTIM, and blanking for the top of the picture can be varied as the blanking width after the reference pulse by the VBLKW register. HBLK width maximum Center HBLK: 13µs HBLK width minimum – 24 – CXA2095S ...
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... HOFF input (In this case, RGB outputs are blanked.) KILLER (1) : Color killer status 0 = Killer OFF status 1 = Killer ON status Note) The following have been added to the CXA2025S. EY-SW: Sub Add 09H, Bit 1 CD-MODE2: Sub Add 09H, Bit 0 HBLK width maximum Center HBLK: 13µs HBLK width minimum – 25 – CXA2095S ...
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... Description of Operation 1. Power-on sequence The CXA2095S does not have an internal power-on sequence. Therefore, all IC operations are controlled by 2 the set microcomputer (I C bus controller). 1) Power-on The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized to the input signal ...
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... Bch video output OFF RGB all blanked Vdrive oscillation stopped Horizontal oscillator frequency standard V countdown auto mode AKB ON Center (Adjust) Vdrive high voltage fluctuation compensation amount max Center (Adjust) Center Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) – 27 – CXA2095S ...
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... F Hex 2. Various mode settings The CXA2095S contains bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once distortion adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data. • ...
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... In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2095S also has a register (H-SIZE) which controls the H size, but the control width is not sufficient for 25% compression. Therefore, external measures must be taken such as switching the H deflection coil. Full mode should be used when performing memory processing and attaching a black border to the video signal ...
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... V size to 67%. Therefore, V-ASPECT is set to enlarge the V size by 8%. AKB reference pulse handling and V blanking are the same as for mode 5) above. 4:3 CRT standard values are used with the V-ASPECT and JMPSW settings changed for the register settings. V-ASPECT = 3FH JMPSW = 1 – 30 – CXA2095S ...
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... V size limited at 75% = 1h: Reference pulse skipping ON (compressed to 50% total) = Adjustable: VBLK width expanded at top and bottom of video image = Adjustable: Compression of top and = Adjustable: bottom of video image = 1h: Reference pulse skipping ON (compressed to 75% total) = Adjustable: VBLK width expanded at top and bottom of video image CXA2095S ...
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... Signal processing The CXA2095S is comprised of sync signal processing, H deflection signal processing, V deflection signal processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I 1) Sync signal processing The Y signals input to Pins 43 and 44 are sync separated by the horizontal and vertical sync separation circuits ...
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... DC level of the R, G and B outputs can be varied by applying voltages independently to Pins 19, 21 and 23 bus register (EY-SW). In other words, the YUV 2 C bus, with the Rch fixed and the G and Bch variable. An auto cut-off 2 C bus. – 33 – CXA2095S 2 C bus bus settings. In this ...
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... When designing the board pattern for TV set, interference from around the power supply and GND should be considered as the RGB and deflection signals output from the CXA2095S are DC direct connected. Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the by- pass capacitor which is inserted between the power supply and GND as near to the pin as possible ...
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... C bus register initial settings” of the Electrical Characteristics Measurement 3.6 3.4 3.2 3.0 2.8 VSIZE = 0 2.6 VSIZE = 1F VSIZE = 3F 2 3.6 3.4 3.2 3.0 2.8 SCORR = 0 2.6 SCORR = 7 SCORR = F 2 3.8 3.6 3.4 3.2 3.0 2.8 VASPECT = 0 2.6 VASPECT = 1F VASPECT = 3F 2 – 35 – V-POSITION V-POSITION = 0 V-POSITION = 1F V-POSITION = Time [ms] V-LIN VLIN = 0 VLIN = 7 VLIN = Time [ms] V-SCROLL VSCROLL = 0 VSCROLL = 1F VSCROLL = Time [ms] CXA2095S ...
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... Time [ms] LO-CPIN 4.1 4.0 3.9 3.8 3.7 3.6 LO-CPIN = 0 3.5 LO-CPIN = 7 LO-CPIN = F 3 Time [ms] 3.6 3.4 3.2 3.0 2.8 2.6 2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3 – 36 – CXA2095S LO-VLIN LO-VLIN = 0 LO-VLIN = 7 LO-VLIN = Time [ms] PIN-PHASE PIN PHASE = 0 PIN PHASE = 7 PIN PHASE = Time [ms] UP-CPIN UP-CPIN = 0 UP-CPIN = 7 UP-CPIN = Time [ms] ...
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... CXA2095S H POSITION SYNC center 44 HSIN µ AFCPIN 36 µ µ DATA SHARPNESS SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = ...
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... CXA2095S SUB CONT DATA BRIGHT SUB-BRIGHT = 3F SUB-BRIGHT = 1F SUB-BRIGHT = DATA (Hex) GAMMA GAMMA 0 GAMMA 1 GAMMA 2 GAMMA ...
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... G, B – CUTOFF 4.0 3.5 3.0 2 DATA (Hex) AKB open loop characteristics 4 3.5 3 2.5 2 1 Voltage applied to Rch, Gch and Bch sample-and-hold capacitance pins [V] – 39 – Rch Gch, Bch IK clamp level CXA2095S ...
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... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN SDIP (PLASTIC) + 0.4 – 0 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SDIP-48P-02 SDIP048-P-0600 LEAD MATERIAL PACKAGE WEIGHT – 40 – CXA2095S 0° to 15° EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER / 42 ALLOY 5.1g ...