CXA3503 Sony Corporation, CXA3503 Datasheet

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CXA3503

Manufacturer Part Number
CXA3503
Description
Driver/Timing Generator for Color LCD Panels
Manufacturer
Sony Corporation
Datasheet
Description
LCD panels LCX032 and LCX033.
circuits and parts by incorporating a RGB driver and
timing generator for video signals onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various settings to
be performed by microcomputer control, etc.
Features
• Color LCD panel LCX032 and LCX033 driver
• Supports NTSC and PAL systems
• Supports 16:9 wide display (letter box and pulse
• Supports Y/color difference and RGB inputs
• Supports OSD input (digital input)
• Power saving function
• Serial interface circuit
• Electronic attenuators (D/A converter)
• Trap and LPF (f0, fc variable)
• COMMON output circuits
• Sharpness function
• 2-point correction circuit
• R, G, B signal delay time adjustment circuit
• D/A output pin (0 to 3V, 8 level output)
• Output polarity inversion circuit
• Supports AC drive for LCD panel during no signal
Applications
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Analog input pin voltage
The CXA3503R is an IC designed to drive the color
This IC greatly reduces the number of peripheral
elimination display)
Color LCD viewfinders
VINA (Pins 57, 58 and 59)
VINA (Pins 3, 69)
VINA (Pin 30)
VINA (Pin 71)
VINA (Pins 70, 72)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Driver/Timing Generator for Color LCD Panels
V
V
V
V
CC
CC
CC
DD
1
2
3
GND – 0.3 to V
1.5 to V
V
5.5
0.9
0.8
15
15
CC
6
CC
1
2 – 4
CC
1 + 0.3 V
Vp-p
Vp-p
V
V
V
V
V
V
– 1 –
• Digital input pin voltage
• Common input pin voltage
• Operating temperature
• Storage temperature
• Allowable power dissipation
Operating conditions
• Supply voltage
• Input voltage
1
2
SIG.C voltage
RGB input signal voltage (Pins 70, 71 and 72)
Y input signal voltage (Pin 71)
R-Y input voltage (Pin 72)
B-Y input voltage (Pin 70)
VIND (other than Pins 5, 10, 14, 15 and 16)
VIND (Pins 5, 10)
VINAD (Pins 14, 15 and 16)
During RGB input
During Y/color difference input
CXA3503R
V
V
V
V
VSIG.C
VRGB
VY
VR-Y
VB-Y
CC
CC
CC
DD
72 pin LQFP (Plastic)
1 – GND1
2 – GND2
3 – GND3
Topr
Tstg
P
– Vss
D
(Ta ≤ 25°C)
0 to 0.622 (0.311 typ.) Vp-p
0 to 0.49 (0.245 typ.) Vp-p
GND, V
0 to 0.5 (0.35 typ.)
V
0 to 0.7 (0.5 typ.)
2
2
SS
V
11.0 to 14.0
11.0 to 14.0
SS
2.7 to 3.6
2.7 to 3.6
5.0 to 6.5
– 0.3 to V
–55 to +150
2
–15 to +75
– 0.3 to +5.5
SS
737
– 0.3 to +5.5 V
E99733A98-PS
DD
+ 0.3 V
Vp-p
Vp-p
mW
1
°C
°C
V
V
V
V
V
V

Related parts for CXA3503

CXA3503 Summary of contents

Page 1

... Driver/Timing Generator for Color LCD Panels Description The CXA3503R designed to drive the color LCD panels LCX032 and LCX033. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc ...

Page 2

... HDO GEN VDO GEN V CONTROL V POSITION PHASE COMPARATOR HSYNC DET H SKEW DET V SEP CK CONTROL MCK CLK +3.0V +3.0V S/P CONV REGISTER DAC Vss CXA3503R 36 G OUT DET 34 R OUT DET 32 B OUT DET 30 SIG.C GND2 29 GND2 28 TST4 27 HDO 26 VDO 25 ...

Page 3

... R DC DET O R signal DC voltage feedback circuit capacitor connection 34 R OUT O R signal output DET O G signal DC voltage feedback circuit capacitor connection 36 G OUT O G signal output — Analog 12.0V power supply CC Description – 3 – CXA3503R Input pin for open status L H ...

Page 4

... I H filter input (for using internal sync separation) 70 B/B-Y I B/B-Y signal input 71 G/Y I G/Y signal input 72 R/R-Y I R/R-Y signal input DWN: DOWN SCAN and UP SCAN, RGT: RIGHT SCAN and LEFT SCAN H: pull-up processing, L: pull-down processing Description – 4 – CXA3503R Input pin for open status ...

Page 5

... GND1 6. GND1 – 5 – CXA3503R Description Amplifies and outputs the sync portion of the video signal input to FIL IN (Pin 69). Sync separation circuit input. Inputs the FIL OUT (Pin 2) output signal via a capacitor. Sync separation output. Positive polarity output in open collector format. ...

Page 6

... R, G and B output DC voltage setting. Connect a 0.01µF capacitor between this pin and GND1. When using a SIG.C of other than V 2/2, input the SIG.C CC voltage from an external source Smoothing capacitor connection for the feedback circuit and B output DC level control. Connect a low-leakage capacitor. CXA3503R ...

Page 7

... GND1 200 69 GND1 – 7 – CXA3503R Description R, G and B signal outputs. The DC level is controlled to match the SIG.C pin voltage. Low output in power saving mode. V 2/2V output when preset. CC Analog 12.0V power supply. (for the RGB output circuits) Analog 12.0V power supply. ...

Page 8

... Equivalent circuit 200 71 72 GND1 – 8 – CXA3503R Description In Y/color difference input mode, input the Y signal to Pin 71, the B-Y signal to Pin 70, and the R-Y signal to Pin 72. In RGB input mode, input the B signal to Pin 70, the G signal to Pin 71 and the R signal to Pin 72. ...

Page 9

... V SS – 9 – CXA3503R Description Digital 3.0V GND. Digital 3.0V power supply. Composite sync/horizontal sync signal input, and serial clock, serial load and serial data inputs for serial communication. Vertical sync signal input. Oscillation circuit output. Oscillation circuit input. ...

Page 10

... Test Pin Description Pin Pin Symbol No. voltage 7 TST1 12 TST2 13 TST3 38 TST5 39 TST6 — 40 TST7 44 TST8 49 TST11 50 TST12 51 TST13 52 TST14 28 TST4 47 TST9 — 48 TST10 56 TST15 Equivalent circuit – 10 – CXA3503R Description Test. Leave these pins open. Test. Connect to GND. ...

Page 11

... MODE (1) DA (000/LSB) SYNC GEN (0) (0) (0) (0) SLSH1 (1) SLSH0 (1) SLSYS2 (0) SLSYS (1) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLTST2 (0) SLDWN (0) SLSYP (1) 0 H-POSITION (10000) 0 HD-POSITION (00000) CXA3503R LSB PICTURE-F0 (00/LSB (0) (0) SLWD (0) SLPL (0) SLVDP (0) SLHDP (0) SLTST1 (0) SLEXVD (0) ...

Page 12

... During no input V8 V17 V30 V31 V33 V35 V69 V70 During Y/color difference input V70 During RGB input V71 V70 During Y/color difference input V70 During RGB input V57 V58 V59 – 12 – CXA3503R =3.0V 12.0V Min. Typ. Max. Unit 27.0 37.0 mA 3.8 5.0 mA 0.90 1.3 mA 23.0 30.0 mA 3.8 5 ...

Page 13

... 3.7 to 3.6V Min. Typ. Max. Unit V 0 0.3 DD 2.6 0.6 0.4 2.6 0.6 0.2 1.0 1.0 3 100 10 40 100 3.0 1.0 2.0 0.3 2.6 0.3 2.6 0.4 V – 0.5 DD 1.0 CXA3503R Applicable pins µA 4 µA µA 5 µA µA 6 µA µA 7 µ µA ...

Page 14

... BLK-LIM = 00h and 1Fh, and assume the BLK-LIM difference from the output DC voltage as 1Fh V 1 and V 2, respectively – 14 – = 0V, SW2 = ON, SW4 = ON, SS Min. Typ. Max. Unit –5.5 2.0 –1.5 0.8 ±1.6 ±2.1 ±4.7 ±5.1 CXA3503R ±0.3 dB 0.6 dB 0.6 –4.5 dB 2.7 –1.0 V 1.2 ±2.7 V ±5.4 ...

Page 15

... V1, V2 and V3, respectively. COLOR GC1 = 20 log (V1/V2) FFh GC2 = 20 log (V3/V2) – 15 – Min. Typ. Max. Unit ±1.2 ±0.6 ±0 1 and V 2, ±0.6 ±1.2 ±1 5.8 6.0 ±0.8 ±4.5 ±4.9 –25 – –1 –30 5.0 6.0 CXA3503R V mV 300 6.2 V ±200 mV ±1.5 V deg deg 1.5 dB –20 dB ...

Page 16

... Input SG6 to TP69 and measure the output amplitude at TP2. Measure the COM output DC voltage when COM-DC = 00h and FFh, and measure the difference from the COM output DC voltage when COM-DC = 80h. – 16 – CXA3503R Min. Typ. Max. Unit 0.85 1.00 1.15 0.41 0.51 0.61 0.15 ...

Page 17

... TP4 from TP3. SEN setup time, activated by the rising edge of SCK. (See Fig. 4.) SDAT setup time, activated by the rising edge of SCK. (See Fig. 4.) – 17 – CXA3503R Min. Typ. Max. Unit 20 31 µA 0.2 0 ...

Page 18

... Measure the transition time of each output. 40pF load: VST, DWN, BLK, RGT, EN, STB and VCK output pins (See Fig. 2.) Measure HCK1/HCK2. 120pF load (See Fig. 3.) Measure the HCK1/HCK2 duty. 120pF load – 18 – CXA3503R Min. Typ. Max. Unit 150 ns 150 210 ns 210 ns 1 µ ...

Page 19

... SDTA D15 D14 D13 D12 D11 D10 ts1 th1 SCK tw1H SEN ts0 Fig. 4. Serial transfer block measurement conditions 90% 10% tTHL T Fig. 3. Cross-point time difference tw1L – 19 – CXA3503R T measurement conditions D15 50% 50% th0 tw2 50% ...

Page 20

... Sine wave video signal; frequency and amplitude variable SG3 25 s SG4 SG5 Waveform 4 – 20 – CXA3503R 3.0Vp-p Amplitude variable Horizontal sync signal 0.1Vp-p 0.1Vp-p High level variable 0V Horizontal sync signal 3V Low level variable Horizontal sync signal ...

Page 21

... SG No. Horizontal sync signal (CSYNC) SG6 Sine wave video signal SG7 Horizontal sync signal (CSYNC) SG8 Waveform 4 4.7ns 1H – 21 – CXA3503R 50mVp-p 0.1Vp-p 0.15Vp-p ...

Page 22

... B DC DET 0.01 30 SIG.C 29 GND2 28 TST4 27 TP27 HDO 26 TP26 VDO 0.1 25 XCLR 24 RPD 23 Vss 22 CKI 21 CKO 3 39p + 15k 47 0.01 TP14 TP16 TP15 CXA3503R 1 TP36 300P SW36 TP34 300P SW34 TP32 300P SW32 TP30 TP24 1k 220p 33k 10k 2 10k 3.3 V22 0.01 6800p ...

Page 23

... Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by BLACK-LIMITER. R-Y signal to Pin 72. Pin 72, CSYNC/HD to Pin 5, and VD to Pin 10. – 23 – CXA3503R 1 1/3) and Vth2 (V 1 2/3). CC ...

Page 24

... B A' Through Through Through B" Output Input Fig. 2 – 24 – HCK1 SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1 Serial data settings Output Input Fig. 3 CXA3503R ...

Page 25

... During 16:9 display the RGB output is specified by BLACK-LIMITER level at a certain timing and goes to BLACK-LIMITER level output. RGB IN 1H inverted signal (internal) 16:9 display signal (internal) RGB OUT 2 + GND2)/2 (or the voltage input to SIG.C CC Set by BLACK-LIMITER – 25 – CXA3503R BLACK-LIMITER WHITE-LIMITER SIG.C WHITE-LIMITER BLACK-LIMITER ...

Page 26

... The serial data PS0, PS1, PS2, PS3, PS4 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the "Description of Serial Control Operation" and "Power Supply and Power Saving Sequence" items. – 26 – CXA3503R ...

Page 27

... Pulse elimination display Display area 4:3 display – 27 – Black display Black display area 28 LINES Display area 172 LINES Black display area 28 LINES 16:9 display CXA3503R ...

Page 28

... MODE (0) DA (000/LSB) SYNC GEN (1) (1) (1) (1) SLSH1 (0) SLSH0 (0) SLSYS2 (0) SLSYS1 (0) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLTST2 (0) SLDWN (0) SLSYP (0) (0) H-POSITION (10000/LSB) (0) HD-POSITION (00000/LSB) CXA3503R LSB D1 D0 (0) (0) PICTURE-F0 (00/LSB (1) (1) SLWD (0) SLPL (0) SLVDP (0) SLHDP (0) SLTST1 (0) SLEXVD (0) ...

Page 29

... This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB limiter level. MSB increases the amplitude MSB increases the amplitude MSB increases the output voltage. MSB advances the phase. – 29 – CXA3503R LSB lowers the point. LSB lowers the point. MSB increases the gain. MSB lowers the ...

Page 30

... This adjusts the picture gain during Y/color difference input. Adjustment from LSB When not using the picture function (OFF), set PICTURE-VOLUME: 00000 (LSB). • DA This adjusts the DA output voltage. See the AC Characteristics for the output level. LPF OFF 2.0MHz 2.7MHz 3.4MHz 3.9MHz 4.9MHz 5.7MHz 6.4MHz – 30 – CXA3503R MSB raises the gain. ...

Page 31

... Supply and Power Saving Sequence". The power-on default for this IC is power saving mode, so the settings should be canceled by serial communication after power-on. D0 Normal operation 1 The respective outputs and corresponding output blocks are stopped. Mode (SYNC GEN) Mode (PS0, PS1, PS2, PS3, PS4) – 31 – CXA3503R ...

Page 32

... SYNC GEN 0 Fig. 1 – 32 – Default LCD display Power-on PS OFF Power-off power- power-off LCD power-on PS0 0 LCD power-off PS1 0 PS3 0 PS4 0 (1) SYNC GEN Power supply CXA3503R LCD Signal Fig. 2. System block diagram CXA3503R ...

Page 33

... PS LCD display PS PS OFF PS ON Power-off power-off PS0 0 PS0 1 LCD power-off PS1 0 PS1 1 PS3 0 PS3 1 PS4 0 (1) PS4 1 SYNC GEN SYNC GEN Power supply CXA3503R LCD Signal Fig. 2. System block diagram CXA3503R / ...

Page 34

... PS0 0 PS0 1 PS0 1 PS1 0 PS1 1 PS1 1 PS3 0 PS3 0 PS3 1 PS4 0 (1) PS4 0 (1) PS4 SYNC GEN SYNC GEN SYNC GEN Power supply HV VV CXA3503R LCD Signal Fig. 2. System block diagram CXA3503R Power-off ...

Page 35

... SHS5 SHS6 Through (Sample-and-hold off Through (Sample-and-hold off) • SLRGT This is the right/left inversion function. This switches the horizontal scan direction of the LCD panel. D7 Scan mode 0 Normal display (right scan) 1 Right/left inverted display (left scan) – 35 – CXA3503R ...

Page 36

... SLFL This function is used to stop output signal polarity inversion. Normally set to polarity inversion. D6 Mode 0 Polarity inversion 1 Polarity inversion stopped D1 Output polarity (VDO) 0 Positive polarity 1 Negative polarity Clamp position – 36 – CXA3503R ...

Page 37

... These set the H position. The horizontal display position is switched by adjusting the HST pulse position using the input horizontal sync signal as the reference. Adjustment is possible in 1 bit = 2fH increments. (1fH = 1 dot) Horizontal sync signal HST Mode 15 steps (30fH) – 37 – HP: 11111 (LSB) HP: 10000 (LSB) HP: 00000 (LSB) 16 steps (32fH) CXA3503R ...

Page 38

... These set the HDO output pulse position. The HDO pulse output position is switched using the input horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments. (1fH = 1 dot) Horizontal sync signal HDO 31 steps (124fH) – 38 – CXA3503R HDP: 00000 (LSB) HDP: 11111 (LSB) ...

Page 39

... R DC DET OUT 0. DET 31 SIG.C 30 0.01 29 GND2 TST4 28 27 HDO 26 VDO 0.1 XCLR 25 24 RPD 23 Vss CKI 22 21 CKO +12V +3V 1 15k 47 0.01 To Serial Controller CXA3503R 1 To LCD Panel 220p 33k 10k 2 10k 3.3 47k 0.01 6800p ...

Page 40

... R DC DET OUT 0. DET SIG.C 30 0.01 29 GND2 TST4 28 HDO 27 26 VDO 0.1 XCLR 25 RPD 24 23 Vss CKI 22 21 CKO +3V 1 15k 47 0.01 To Serial Controller CXA3503R 1 To LCD Panel 220p 33k +12V 10k 2 10k 3.3 47k 0.01 6800p ...

Page 41

... GND1 and GND2/3 pins to the lowest potential applied to this IC; do not leave SS these pins open. The voltages applied to the power supply pins should be as follows. = GND1 = GND2/3 ≤ pattern in order to reduce impedance as much as possible lower than V to I/O pins ≤ – 41 – CXA3503R should not be SS ...

Page 42

... SONY CODE EIAJ CODE JEDEC CODE 72PIN LQFP (PLASTIC) 12.0 ± 0.3 10.0 ± 0.2 0.65 ± 0 0.2 ± 0.08 0.08 M 0.1 ± 0.1 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-72P-L111 LEAD MATERIAL P-LQFP72-10X10-0.5 PACKAGE MASS – 42 – CXA3503R 14.5 ± 0.2 A 0.15 ± 0.05 0.1 EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g ...

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