CXA3516 Sony Corporation, CXA3516 Datasheet - Page 80

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CXA3516

Manufacturer Part Number
CXA3516
Description
3-channel 8-bit 165MSPS A/D Converter Amplifier PLL
Manufacturer
Sony Corporation
Datasheet

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1/2 clock
ADC Timing Diagram
The timing diagram above supposes DMUX Parallel Data out Mode. It is possible for the post-stage scaling IC
to acquire data by using a 1/2 clock. The output delay time in this mode is the same as that in DMUX Interleaved
Data out Mode.
Clock
Data
XCLK
CLK
1/2XCLK
1/2CLK
2.3ns to 2.6ns to 3.2ns
Td_7
min.
T
T – 2.2ns
min.
typ.
– 80 –
max.
0.9ns to 1.2ns to 1.6ns
Td_6
min.
T + 1.3ns
typ.
min.
max.
2.0V
0.8V
T
T
T
T
R_CLK
F_CLK
R_DATA
F_DATA
2.0V
0.8V
T
T
2.0V
0.8V
R_CLK
F_CLK
0.8ns
1.0ns
0.9ns
0.9ns
min.
min.
0.8ns
1.0ns
min.
1.4ns
1.5ns
1.2ns
1.2ns
typ.
typ.
1.4ns
1.5ns
typ.
2.3ns
2.8ns
2.0ns
2.0ns
max.
max.
CXA3516R
2.3ns
2.8ns
max.

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