ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 30

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.0
The input pins, LORS and BORS, select whether the Local (LSTo0-15) and Backplane (BSTo0-15) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW). In the latter case (i.e., always driven), a high impedance state, if required on a per-channel basis, is invoked
through an external interface circuit controlled by the LCSTo0-1/BCSTo0-1 signals.
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-15/BSTo0-15, to transmit bi-state
channel data with per-channel high impedance determined by external circuits under the control of the
LCSTo0-1/BCSTo0-1 outputs.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-15/BSTo0-15, of the device to
invoke a high impedance output on a per-channel basis when required as controlled by the LE/BE bit.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation,
e.g., following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE.
Bit Advancement = -2
Bit Advancement = -4
Bit Advancement = -6
Bit Advancement = 0
(input pin)
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps
RESET
Port High-Impedance Control
BSTo/LSTo0-15
BSTo/LSTo0-15
BSTo/LSTo0-15
BSTo/LSTo0-15
System Clock
0
0
1
1
1
1
1
131.072 MHz
(Default)
FP8o
(input pin)
ODE
Table 2 - Local and Backplane Output Enable Control Priority
X
X
0
0
1
1
1
Bit 1
Bit 1
Bit 1
Ch255
Register bit)
Bit 1
Ch255
(Control
OSB
Bit 0
X
X
X
X
0
0
1
Ch255
Bit 0
Ch255
Bit 0
Zarlink Semiconductor Inc.
Memory bit)
Connection
Backplane
(Local /
Bit 0
ZL50050
LE/BE
X
X
X
X
X
X
0
Bit 7
30
Bit 7
Bit Advancement, 0
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
LORS/BORS
Bit 7
(input pin)
Bit 7
0
1
0
1
0
1
0
Bit 6
Bit 6
Ch0
Bit 6
LSTo0-15/
BSTo0-15
Ch0
HIGH
HIGH
HIGH
HIGH
HI-Z
HI-Z
HI-Z
Bit 6
Ch0
Bit 5
Ch0
Bit 5
Bit 5
LCSTo0-1/
BCSTo0-1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Bit 5
Data Sheet
Bit 4
Bit 4