ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 54

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Bit
1:0
8
7
6
5
4
3
2
MODE32B
Reserved
C8IPOL
COPOL
MS[1:0]
Name
FPW
MBP
OSB
Reset
Value
0
0
0
0
0
0
0
0
Frame Pulse Width
When LOW, the user must apply a 122 ns frame pulse on FP8i; the FP8o pin will
output a 122 ns wide frame pulse; FP16o will output a 61ns wide frame pulse.
When HIGH, the user must apply a 244ns frame pulse on FP8i; the FP8o pin will
output a 244 ns wide frame pulse; FP16o will output a 122 ns wide frame pulse.
Backplane 32 MHz Mode
When LOW, Backplane streams BSTi0-15 and BSTo0-15 may be individually
programmed for data rates of 2, 4, 8, or 16 Mbps.
When HIGH, Backplane streams BSTi0-7 and BSTo0-7 operate at 32.768 Mbps
only and BSTi8-15 and BSTo8-15 are unused.
8 MHz Input Clock Polarity
The frame boundary is aligned to the falling or rising edge of the input clock.
When LOW, the frame boundary is aligned to the clock falling edge.
When HIGH, the frame boundary is aligned to the clock rising edge.
Output Clock Polarity
When LOW, the output clock has the same polarity as the input clock.
When HIGH, the output clock is inverted.
This applies to both the 8 MHz (C8o) and 16 MHz (C16o) output clocks.
Memory Block Programming
When LOW, the memory block programming mode is disabled.
When HIGH, the connection memory block programming mode is ready to program
the Local Connection Memory (LCM) and the Backplane Connection Memory
(BCM).
Output Stand By
This bit enables the BSTo0-15 and LSTo0-15 serial outputs.
When LOW, BSTo0-15 and LSTo0-15 are driven HIGH or high impedance,
dependent on the BORS and LORS pin settings respectively, and BCSTo0-1 and
LCSTo0-1 are driven low.
When HIGH, BSTo0-15, LSTo0-15, BCSTo0-1 and LCSTo0-1 are enabled.
Reserved
Must be set to 0 for normal operation
Memory Select Bits
These three bits select the connection or data memory for subsequent microport
memory access operations:
00 selects Local Connection Memory (LCM) for read or write operations.
01 selects Backplane Connection Memory (BCM) for read or write operations.
10 selects Local Data Memory (LDM) for read-only operation.
11 selects Backplane Data Memory (BDM) for read-only operation.
Output Control with ODE pin and OSB bit
Table 19 - Control Register Bits (continued)
ODE Pin
0
1
1
Zarlink Semiconductor Inc.
ZL50050
OSB bit
54
X
0
1
Description
BSTo0-15, LSTo0-15
Disabled
Disabled
Enabled
Data Sheet