ZL50051 ZARLINK [Zarlink Semiconductor Inc], ZL50051 Datasheet - Page 35

• Manufacturer Part Number: ZL50051
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.0
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
0000
0001
0023
0063
0083
00A3
014D
1001
3FFF
12:8
7:0
Bit
13
A14-A0
H
H
H
H
H
H
H
H
H
- 0042
- 0082
- 00A2
- 00C2
Internal Register Mappings
BSAB[4:0]
BCAB[7:0]
Name
BE
H
H
H
H
Table 11 - BCM Bits for Source-to-Backplane Switching (continued)
Control Register, CR
Block Programming Register, BPR
Local Input Bit Delay Register 0 - 31, LIDR0 - 31
Backplane Input Bit Delay Register 0 - 31, BIDR0 - 31
Local Output Advancement Register 0 - 31, LOAR0 - 31
Backplane Output Advancement Register 0 - 31, BOAR0 - 31
Memory BIST Register, MBISTR
Bit Rate Register, BRR
Device Identification Register, DIR
Backplane Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when BMM is set HIGH.
Source Channel Address Bits / Message Mode Data
The binary value of these 8 bits represents the input channel number when BMM is set
LOW.
Transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
Table 12 - Address Map for Registers (A14 = 0)
Zarlink Semiconductor Inc.
ZL50051/3
35
Description
Register
Data Sheet