ZL50073GAC ZARLINK [Zarlink Semiconductor Inc], ZL50073GAC Datasheet - Page 19

• Manufacturer Part Number: ZL50073GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps)
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

These additional input clocks and frame pulses can be used as alternative clock sources for the input streams,
output streams, and output clocks / frame pulses. The input streams’ clock sources are controlled by the ISSRC1-0
(bits 1 - 0) in the Group Control Registers (GCR). The output streams’ clock sources are controlled by the
OSSRC1-0 (bits 17 - 16) in the Group Control Registers (GCR). The output clocks’ / frame pulses’ clock sources
are controlled by the CKO3SRC1-0 (bits 22-21), CKO2SRC1-0 (bits 15-14), CKO1SRC1-0 (bits 8-7), and
CKO0SRC1-0 (bits 1-0) in the Output Clock Control Register (OCCR). The clock sources can be set to either the
internal system clock or one of the three input clock signals. These are used to provide a direct interface to jittery
peripherals.
When the internal system clock is not used as the clock source, there are limitations to the data rate and the output
clock rate. For all the input and output stream groups that do not use the internal system clock as their clock source,
the data rate is limited to be no higher than the selected clock source’s rate (e.g. if CKi1 runs at 16.384 MHz and it
is selected as the clock source for input stream group 3, then the maximum data rate of STiA3, STiB3, STiC3, and
STiD3 is 16.384Mbps). Similarly, for all the output clocks that do not use the internal system clock as their clock
source, the clock rate is limited to be no higher than the selected clock source’s rate (e.g. if CKi1 runs at
32.768 MHz and it is selected as the clock source for output clock CKo0, then the maximum clock rate of CKo0 is
32.768 MHz).
3.0
There are four output timing pairs, CKo3 - 0 and FPo3 - 0. By default these signals generate ST-BUS, negative
timing, and use the internal system clock as reference clock source. Their default clock rates are 65.536 MHz for
CKo0, 32.768 MHz for CKo1, 16.384 MHz for CKo2, and 8.192 MHz for CKo3. Their properties can also be
individually programmed in the Output Clock Control Register (OCCR) to control the frame pulse format
(ST-BUS/GCI-Bus), frame pulse polarity, clock polarity, clock rate (8.192 MHz, 16.384 MHz, 32.768 MHz or
65.536 MHz), and reference clock source. Refer to Section 14.6 for programming details. Note that the reference
clock source can be set to either the internal system clock or one of the three input clock signals. If one of the three
input clock signals is selected as the reference source, the output clock cannot be programmed to generate a
higher clock frequency than the reference source. As each output timing pair has its own bit settings, they can be
set to provide different output timings. For 65.536 MHz output clock, the total loading on the output should not
be larger than 10pF.
4.0
To be able to interface with external buffers, the output signals can be set to enter a high impedance or drive high
state on a per-channel basis. The Per Channel Function (bits 31 - 29) in the Connection Memory Bits can be set to
001 to drive the channel output high, or to 000, 110 or 111 to set the channel into a high impedance state.
5.0
The Group Control Registers (GCR) are used to adjust the input delay and output advancement for each input and
output data groups. Each group is independently programmed.
5.1
The input sampling point delay programming feature provides users with the flexibility of handling different wire
delays when incoming traffic is from different sources.
By default, all input streams have zero delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The nominal input sampling point with zero delay is at the 3/4 bit time.
The input delay is enabled by the Input Sample Point Delay (bit 8 - 4) in the Group Control Registers 0 - 31 (GCR0
- 31) as described in Section 14.4 on page 43. The input sampling point delay can range from 0 to 7 3/4 bit delay
with a 1/4 bit resolution on a per group basis.
Input Sampling Point Delay Programming
Output Clock (CKo) and Output Frame Pulse (FPo) Timing
Output Channel Control
Data Input Delay and Data Output Advancement
Zarlink Semiconductor Inc.
ZL50073
19
Data Sheet