ZL50073GAC ZARLINK [Zarlink Semiconductor Inc], ZL50073GAC Datasheet - Page 49

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ZL50073GAC

Manufacturer Part Number
ZL50073GAC
Description
32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps)
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
10 - 9
CKO2
SRC1
8 - 7
External Read/Write Address: 40284
Reset Value: 060D1C3C
Bit
12
11
31
15
0
6
5
CKO2
SRC0
30
14
0
Name
CKO1
CKO1
RATE
POL1
POL1
POL0
SEL0
GCO
CKO
SRC
FPO
1 - 0
1 - 0
FPO
SEL1
GCO
29
13
0
POL1
H
FPO
28
12
Frame Pulse Polarity Selection for FPo1
When this bit is low, FPo1 is set for active high.
When this bit is high, FPo1 is set for active low.
Clock Polarity Selection for CKo1
When this bit is low, CKo1 is set for the positive clock edge.
When this bit is high, CKo1 is set for the negative clock edge.
Output Clock Rate for CKo1 and FPo1
The output clock rate can not exceed the selected clock source rate. All rates are avail-
able when the internal system clock is selected as clock source.
Output Clock Source for CKo1 and FPo1
GCI-Bus Selection for FPo0
When this bit is low, FPo0 is set for ST-BUS mode.
When this bit is high, FPo0 is set for GCI-Bus mode.
Frame Pulse Polarity Selection for FPo0
When this bit is low, FPo0 is set for active high.
When this bit is high, FPo0 is set for active low.
0
Table 27 - Output Clock Control Register (continued)
POL1
SEL3
GCO
CKO
27
11
CKO1RATE1 - 0
CKO1SRC1 - 0
H
RATE1
CKO1
POL3
FPO
00
01
10
00
01
10
11
11
26
10
RATE0
CKO1
POL3
CKO
25
9
Zarlink Semiconductor Inc.
RATE1
ZL50073
CKO3
CKO1
SRC1
24
8
16.384 MHz
32.768 MHz
65.536 MHz
8.192 MHz
49
CKo1
Output Timing Source
Internal System Clock
RATE0
CKO3
CKO1
SRC0
23
7
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
Description
CKO3
SRC1
SEL0
GCO
22
6
CKO3
SRC0
POL0
FPO
21
5
120 ns
POL0
SEL2
GCO
CKO
FPo1
60 ns
30 ns
15 ns
20
4
RATE1
CKO0
POL2
FPO
19
3
RATE0
CKO0
POL2
CKO
18
2
RATE1
Data Sheet
CKO2
CKO0
SRC1
17
1
RATE0
CKO2
CKO0
SRC0
16
0

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