ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet

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... Buffer Compensation for 16-128 ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Figure 1 - ZL50110/11/14 High Level Overview Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. 128, 256 and 1024 Channel CESoP ...

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... Leased Line support over packet networks • Multi-Tenant Unit access concentration • TDM over Cable • Fibre To The Premises G/E-PON • Layer 2 VPN services • Customer-premise and Provider Edge Routers and Switches • Packet switched backplane applications ZL50110/11/14 2 Zarlink Semiconductor Inc. Data Sheet ...

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... Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) - draft-ietf- pwe3-cesopsn The ZL50110/11/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports. The ZL50110/11/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality ...

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... Device Line Up There are three products within the ZL50110/11/14 family, with capacity as shown in the following table: Device TDM Interfaces ZL50114 4 T1 streams or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps ZL50110 8 T1 streams or 8 MVIP/ST-BUS streams at 2 ...

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... Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.1 ZL50111 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 ZL50110 Variant TDM stream connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.3 ZL50114 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.4 TDM Signals Common to ZL50111, ZL50110 and ZL50114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 Packet Interfaces 3.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.6 System Function Interface ...

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... PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.6 Packet Interface Timing 11.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.6.3 GMII Transmit Timing 11.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.6.5 TBI Interface Timing 11.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.7 External Memory Interface Timing 11.8 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.9 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ZL50110/11/14 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...

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... High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.1.1 External Memory Interface - special considerations during layout 13.1.2 GMAC Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.3 TDM Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3 Mx_LINKUP_LED Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.1 External Standards/Specifications 14.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ZL50110/11/14 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 12 - ZL50110/11/14 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 13 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 14 - ZL50110/11/14 Packet Format - Structured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 15 - Channel Order for Packet Formation Figure 16 - ZL50110/11/14 Packet Format - Unstructured Mode Figure 17 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 18 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 19 - External Memory Requirement for ZL50111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 20 - External Memory Requirement for ZL50110 ...

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... Figure 49 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 50 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ZL50110/11/14 List of Figures 9 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 19 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 22 - TDM Services Offered by the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23 - Some of the TDM Port Formats Accepted by the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . 51 Table 24 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 25 - Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 26 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 27 - TDM ST-BUS Master Timing Specification ...

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... DC Electrical Characteristics Table and Output Levels Table 98 Section 13.3 ZL50110/11/14 Change Clarified ZL50111 supports 3 MII ports, ZL50110/4 support 2 MII ports. Added external pull-up/pull-down resistor recommendations for SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK. Added Section 6.3 SYSTEM_CLK Considerations. Change Clarified data sheet to indicate ZL5011x supports clock recovery in both synchronous and asynchronous modes of operation ...

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... Body Size: • Ball Count: • Ball Pitch: • Ball Matrix: • Ball Diameter: • Total Package Thickness: The ZL50110 will be packaged in a PBGA device. Features: • Body Size: • Ball Count: • Ball Pitch: • Ball Matrix: • Ball Diameter: • ...

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... GND RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TDI IC_GND CPU_ADD A[50] A[55] A[56] A[61] DE[ Figure 2 - ZL50111 Package View and Ball Positions ZL50110/11/14 TDM_CLK TDM_CLKi TDM_CLKi TDM_CLK GND TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ 7] o[10] [10] [11] ...

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... ZL50110 Package view from TOP side. Note that ball A1 is non-chamfered corner GND TDM_STo TDM_CL TDM_STo TDM_STo TDM_STi[ TDM_STo TDM_STi[ [1] Ko[3] [4] [ TDM_FR TDM_STo TDM_STi[ TDM_CL TDM_STi[ ...

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... TA[63] AE RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TR TA[35] TA[40] TA[48] TA[54] TA[57] TA[62 GND RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TDI IC_GND CPU_AD TA[50] TA[55] TA[56] TA[61] ODE[ Figure 4 - ZL50114 Package View and Ball Positions ZL50110/11/14 N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C ...

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... B7 TDM_STo[6] † B8 TDM_CLKo[8] † B9 TDM_CLKi[9] † B10 TDM_STo[10] † B11 TDM_STi[10] † B12 TDM_CLKi[12] † B13 TDM_STo[12] ZL50110/11/14 Ball Signal Name Number † B14 TDM_STi[13] † B15 TDM_CLKi[15] † B16 TDM_STi[15] † B17 TDM_STi[17] † B18 TDM_CLKi[18] † B19 TDM_CLKo[20] † ...

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... F21 GND † F22 TDM_CLKi[31] † F23 TDM_CLKo[29] † F24 TDM_STo[28] † F25 TDM_CLKo[31] † F26 M1_LINKUP_LED G1 RAM_DATA[21] G2 RAM_DATA[18] G3 RAM_DATA[16] ZL50110/11/14 Ball Signal Name Number G4 RAM_DATA[14] G5 RAM_DATA[11] G6 RAM_DATA[8] † G21 TDM_STo[31] † G22 TDM_STo[30] G23 M1/2_LINKUP_LED G24 M0/3_LINKUP_LED G25 M1_GIGABIT_LED G26 ...

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... GND N16 GND N18 VDD_IO N21 M1_GTX_CLK N22 GND N23 M1_TXER N24 M1_RXD[2] N25 M1_RXD[3] N26 GND P1 RAM_ADDR[9] P2 RAM_ADDR[10] P3 RAM_ADDR[11] ZL50110/11/14 Ball Signal Name Number P4 RAM_ADDR[13] P5 RAM_ADDR[16] P6 GND P9 VDD_IO P11 GND P12 GND P13 GND P14 GND P15 GND P16 GND ...

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... Y6 VDD_CORE Y21 VDD_CORE Y22 M0_TXD[1] Y23 M0_TXD[4] Y24 M0_RBC0 Y25 M0_COL Y26 M0_RXD[1] AA1 GPIO[1] AA2 GPIO[7] AA3 GPIO[8] ZL50110/11/14 Ball Signal Name Number AA4 GPIO[15] AA5 RAM_DATA[39] AA6 GND AA7 RAM_DATA[45] AA8 RAM_DATA[52] AA9 VDD_CORE AA10 JTAG_TMS AA11 CPU_ADDR[2] AA12 ...

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... CPU_DATA[17] AF23 CPU_DATA[19] AF24 CPU_DATA[26] AF25 CPU_DATA[31] AF26 GND † Not Connected on ZL50110 and ZL50114 - leave open circuit. ‡ Not Connected on ZL50114 - leave open circuit. N/C - Not Connected - leave open circuit Internally Connected - leave open circuit. IC_GND - tie to ground IC_VDD_IO - tie to VDD_IO 20 Zarlink Semiconductor Inc ...

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... Table 2 - TDM Interface ZL50111 Stream Pin Definition ZL50110/11/14 Package Balls D26 [15] B16 TDM port serial data input streams. For E25 [14] D14 different standards these pins are given D25 [13] B14 different identities: C26 [12] ...

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... Table 2 - TDM Interface ZL50111 Stream Pin Definition (continued) ZL50110/11/14 Package Balls G21 [15] E14 TDM port serial data output streams. For G22 [14] A15 different standards these pins are given E26 [13] A14 different identities: F24 [12] ...

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... streams active (bits [1:0]), with 537 channels per stream - 1074 total channels streams active (bits [1:0]), with 699 channels per stream - 1398 total channels. Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used. ZL50110/11/14 Package Balls F25 [15] A16 TDM port clock outputs ...

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... Table 3 - TDM Interface ZL50110 Stream Pin Definition Note: Speed modes: 2.048 Mbps - all 8 streams active (bits [7:0]), with 32 channels per stream - 256 total channels. 8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels streams active (bits [1:0]), with 98 channels per stream - 196 total channels. ...

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... streams active (bits [1:0]), with 98 channels per stream - 196 total channels. Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used. ZL50110/11/14 Package Balls C5 TDM port serial data input streams. For ...

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... TDM Signals Common to ZL50111, ZL50110 and ZL50114 Signal I/O TDM_CLKi_REF TDM_CLKo_REF O E6 TDM_FRMi_REF TDM_FRMo_REF O B1 Table 5 - TDM Interface Common Pin Definition ZL50110/11/14 Package Balls TDM port reference clock input for backplane operation TDM port reference clock output for backplane operation TDM port reference frame input ...

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... PLL_PRI OT U1 PLL_SEC OT V1 Table 6 - PAC Interface Package Ball Definition ZL50110/11/14 Package Balls Primary reference clock input. Should be driven by external clock source to provide locking reference to internal / optional external DPLL in TDM master mode. Also provides PRS clock for RTP timestamps in synchronous modes. ...

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... For the ZL50111 variant the packet interface is capable of either 3 MII interfaces, 2 GMII interfaces or 2 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. The ZL50110 variant has either 2 MII interfaces, 2 GMII interfaces or 2 TBI (1000 Mbps) interfaces. Ports 2 and 3 are not available on the ZL50110 device. ...

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... MII ports. It has a minimum period of 400ns (maximum freq. 2.5 MHz), and is independent of the TXCLK and RXCLK. MII management data I/O. Common for all four MII ports 2.5 MHz bi-directional between the ZL50110/11/14 and the Ethernet station management entity. Data is passed synchronously with respect to M_MDC. MII Port 0 ...

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... V25 M0_RXD[8] M0_RXER / I D V26 M0_RXD[9] Table 9 - MII Port 0 Interface Package Ball Definition (continued) ZL50110/11/14 MII Port 0 Package Balls TBI - M0_RBC0. Used as a clock when in TBI mode. Accepts 62.5 MHz, and is 180°C out of phase with M0_RBC1. each rising edge of M1_RBC1 and M1_RBC0, resulting in 125 MHz sample rate ...

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... Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/MII - M0_TXER Transmit Error. Transmitted synchronously with respect to M0_TXCLK, and active high. When asserted (with M0_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M0_TXD[9] Transmit Data. Clocked on rising edge of M0_GTXCLK. ...

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... Signal I/O M1_LINKUP_LED O G23 on ZL50110/4 F26 on ZL50111 M1_ACTIVE_LED O AB25 M1_GIGABIT_LED O G25 M1_REFCLK I D M22 M1_RXCLK I U M23 M1_RBC0 I U U26 M1_RBC1 I U T25 M1_COL I D R25 Table 10 - MII Port 1 Interface Package Ball Definition ZL50110/11/14 MII Port 1 Package Balls LED drive for MAC 1 to indicate port is linked up ...

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... M1_TXCLK I U L22 M1_TXD[7:0] O [7] [6] [5] [4] M1_TXEN / O P23 M1_TXD[8] Table 10 - MII Port 1 Interface Package Ball Definition (continued) ZL50110/11/14 MII Port 1 Package Balls M25 [3] N25 Receive Data. Only half the bus (bits [3:0]) P26 [2] N24 are used in MII mode. Clocked on rising M24 [1] R26 ...

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... MII Port 1 Package Balls GMII/MII - M1_TXER Transmit Error. Transmitted synchronously with respect to M1_TXCLK, and active high. When asserted (with M1_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M1_TXD[9] Transmit Data. Clocked on rising edge of M1_GTXCLK. GMII/TBI only - Gigabit Transmit Clock Output of a clock for Gigabit operation at 125 MHz ...

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... Active high. Transmit Error. Transmitted synchronously with respect to M2_TXCLK, and active high. When asserted (with M2_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame. MII Port 3 - ZL50111 variant only they are mutually exclusive. ...

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... Remains asserted until the end of the packet transmission. Active high. Transmit Error. Transmitted synchronously with respect to M3_TXCLK, and active high. When asserted (with M3_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame. 36 Zarlink Semiconductor Inc. Data Sheet ...

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... RAM_PARITY[7:0] IU/ [7] [6] OT [5] [4] Table 13 - External Memory Interface Package Ball Definition ZL50110/11/14 Package Balls AD7 [31] K3 Buffer memory data. Synchronous to rising AE6 [30] K4 edge of SYSTEM_CLK. AF5 [29] J1 AB8 [28] J2 AC7 [27] J3 AD6 [26] J4 AE5 ...

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... RAM_BW_C RAM_BW_D RAM_BW_E RAM_BW_F RAM_BW_G RAM_BW_H RAM_RW Table 13 - External Memory Interface Package Ball Definition (continued) ZL50110/11/14 Package Balls R4 [9] P1 Buffer memory address output. T2 [8] N4 Synchronous to rising edge of T1 [7] N3 SYSTEM_CLK [4] ...

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... CPU_OE to asynchronously enable the CPU_DATA output during a read, including DMA read. CPU Write Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU writes from the processor to registers within the ZL50110/11/14. Asserted one clock cycle after CPU_TS_ALE. ...

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... CPU_DATA. The data is then read by the host on the following rising edge of CPU_CLK. For a write, is asserted when the ZL50110/11/14 is ready to accept data from the host. The data is written on the rising edge of CPU_CLK following the assertion. Returns to tri-state from the negative clock edge of CPU_CLK following the de-assertion of CPU_CS ...

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... See Section 6.3. System Reset Input. Active low. The system reset is asynchronous, and causes all registers within the ZL50110/11/ reset to their default state. Recommend external pull-up. System Debug Enable. This is an asynchronous signal that, when de-asserted, prevents the software ...

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... Y3 internal register, so customer can set AC2 [5] AB1 user-defined parameters. Bits [4:0] reserved AC1 [ startup or reset for memory TDL setup. AB2 [3] W4 See the ZL50110/11/14 Programmers Model Y4 [2] V5 for more details. Recommend 5 kohm W5 [1] AA1 pulldown on these signals. AA3 [0] W3 AF6 Test Mode input - ensure these pins are tied AB9 to ground for normal operation ...

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... P12 P16 R13 T5 T14 AA6 AF13 VDD_CORE F7 F20 AA13 A1VDD T6 Table 19 - Power and Ground Package Ball Definition ZL50110/11/14 Package Balls Internally Connected. Tie to GND. Internally Connected. Tie to VDD_IO. Package Balls J10 J11 J12 J14 J15 J16 J18 K9 K18 L18 M9 M18 ...

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... TDM business. The ZL50110/11/14 is capable of handling circuit emulation of both structured T1, E1, and J2 links (e.g., for support of fractional circuits) and unstructured (or clear channel) T1, E1, J2, T3, E3 and STS-1 links. The device handles the data-plane requirements of the provider edge inter-working function (with the exception of the physical interfaces and line interface units) ...

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... BBDLC and the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections from several BBDLC are aggregated in the CO using a larger ZL50110/11/14 variant, converted back to TDM circuits, and connected to a class 5 switch destined towards the PSTN. ...

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... Gigabit Ethernet (GE) fiber, that may be owned by the carrier or accessed through a service provider. The ZL50110/11/14 would sit in a box either external to the base stations, or integrated in them, and would transparently carry multiple T1/E1s to the base station controllers using CESoP connections. At the base station controller location another ZL50110/11/14 would terminate the CESoP connection and provide the T1/E1 line to the controllers ...

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... The first line card supports T1/E1 lines, containing up to 1024 DS0, for Nx64 kbps structured data transfer (SDT) CESoP connections. The T1/E1 lines are broken down into DS0 channels on an H.110 bus. The ZL50110/11/14 establishes CESoP connections, with each connection taking a number of DS0 channels from the H.110 bus. ...

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... Functional Description The ZL50110/11/14 family provides the data-plane processing to enable constant bit rate TDM services to be carried over a packet switched network, such as an Ethernet MPLS network. The device segments the TDM data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far end ...

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... Block Diagram A diagram of the ZL50110/11/14 device is given in Figure 12, which shows the major data flows between functional components. TDM Interface Clock Recovery Data Flows Control Flows Figure 12 - ZL50110/11/14 Data and Control Flows 5.2 Data and Control Flows There are numerous combinations that can be implemented to pass data through the ZL50110/11/14 device depending on the application requirements ...

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... This section describes the flows between the TDM interface, the packet interface and the Task Manager which are the main flow routes used in the ZL50110/11/14 family. For example, the TDM->TM flow is used in flow types and 6, and the TM->PKT flow is used in flow types 1, 3, and 9. ...

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... Structured TDM Port Data Formats The ZL50110/11/14 is programmable such that the frame/clock polarity and clock alignment can be set to any desired combination. Table 23 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and Generic (synchronous mode only), for more information see the relevant specifications shown. There are many additional formats for TDM transmission not depicted in Table 23, but the flexibility of the port will cover almost any scenario ...

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... TDM_CLKi[31:0] TDM_CLKiP TDM_CLKiS Figure 13 - Synchronous TDM Clock Generation When the ZL50110/11/14 is acting as a slave device, the common clock and frame pulse signals are taken from an external device providing the TDM master function. 5.3.3.2 Asynchronous TDM Clock Generation Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be controlled to recover the clock from the original TDM source depending on the timing algorithm used ...

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... The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet standard minimum packet size. Where this is likely to be the case, the header or data must be padded (as shown in Figure 14 and Figure 16) to ensure the packet is large enough. This padding is added by the ZL50110/11/14 for most applications. ...

Page 54

... NOTE: No alignment of the octets with the T1 framing structure can be assumed. Header N octets of data from unstructured stream NOTE: No frame or channel alignment Figure 16 - ZL50110/11/14 Packet Format - Unstructured Mode ZL50110/11/ ...

Page 55

... ZL50110/11/14 family: UDP, RTP, L2TP, CESoPSN and SAToP. The Protocol Engine can add a header to the datagram containing bytes. This header is largely static information, and is programmed directly by the CPU ...

Page 56

... Two schemes are employed, depending on the availability of a common reference clock at each provider edge unit, within the ZL50110/11/14 - differential and adaptive. The clock recovery itself is performed by software in the external processor, with support from on-chip hardware to gather the required statistics ...

Page 57

... The qualitiy of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator. Please review application note ZLAN-159 “External Component Selection” before choosing an oscillator. ZL50110/11/14 ZL5011x destination ...

Page 58

... The receive latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to compensate for packet network PDV. The ZL50110/11/14 is capable of creating an extremely low latency connection, with end to end delays of less than 0.5 ms, depending on user configuration. 7.2 Loopback Modes The ZL50110/11/14 devices support loopback of the TDM circuits and the circuit emulation packets ...

Page 59

... Therefore the device allows the connection Mbytes of synchronous ZBT-SRAM. The following charts show how much memory is required by the ZL50111 (32 T1 streams) and the ZL50110 (8 T1 streams) for a variety of packet sizes (expressed in number of frames of TDM data) and jitter buffer sizes assumed that each packet contains a full Ethernet/MPLS/MPLS/RTP/CESoPSN header ...

Page 60

... GIGABIT Ethernet - Recommended Configurations NOTE: In GMII/TBI mode only 1 GMAC port may be used. The second GMAC port is for redundancy purposes only. This section outlines connection methods for the ZL50110/11/ Gigabit Ethernet environment recommended to ensure optimum performance. Two areas are covered: • ...

Page 61

... GMII ZL5011x TDM Figure 21 - Gigabit Ethernet Connection - Central Ethernet Switch TDM data and control packets are directed to the appropriate ZL50110/11/14 device through the Ethernet Switch. There is no limit on the number of ZL50110/11/14 devices that can be connected in this configuration. ZL50110/11/14 Network Switch Ethernet ...

Page 62

... The central Ethernet Switch configuration can be extended to include a redundant switch connected to the second ZL50110/11/14 GMII port. One port should be used for all the TDM-to-Packet and Packet-to-TDM data with the other port idle. If the current port fails then data must be transferred to the spare port. ...

Page 63

... JTAG (IEEE1149) Test Access Port • 3.3 V I/O Supply rail with 5 V tolerance • 1.8 V Core Supply rail • Fully compatible with MT90880/1/2/3 Zarlink product line ZL50110/11/14 > 100 µ Figure 23 - Powering Up the ZL50110/11/14 63 Zarlink Semiconductor Inc. Data Sheet I/O supply (3.3 V) Core supply (1 ...

Page 64

... Test Modes Operation 7.11.1 Overview The ZL50110/11/14 family supports the following modes of operation. 7.11.1.1 System Normal Mode This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access Port and Boundary Scan Architecture ...

Page 65

... MTIE requirements for these specifications. In structured mode with the ZL50110/11/14 device operating as a master the DPLL is used to provide clock and frame reference signals to the internal and external TDM infrastructure. In structured mode, with the ZL50110/11/14 device operating as a slave, the DPLL is not used ...

Page 66

... See Section 8.7 for further details. Limitations depend on the users programmed values, so the DPLL must be programmed properly to meet Stratum 3, or Stratum 4/4E. The Application Program Interface (API) software that accompanies the ZL50110/11/14 family can be used to automatically set up the DPLL for the appropriate standard requirement. ...

Page 67

... Locking time is very difficult to determine because it is affected by many factors including: • initial input to output phase difference • initial input to output frequency difference ZL50110/11/14 67 Zarlink Semiconductor Inc. Data Sheet ...

Page 68

... There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter master clock period is possible holdover mode huge amount of jitter had been present prior to entering holdover, then an additional 2 ns p-p is possible. ZL50110/11/ internal Tapped Delay Line (TDL). The DPLL 68 Zarlink Semiconductor Inc ...

Page 69

... Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement. Additionally the speed at which the change occurs is also critical. A large step change in output frequency is undesirable. The rate of change is programmable using the skew register maximum of 15 125 µs (124 ppm). ZL50110/11/14 Figure 24 - Jitter Transfer Function 69 Zarlink Semiconductor Inc. ...

Page 70

... Memory Map and Register Definitions All memory map and register definitions are included in the ZL50110/11/14 Programmers Model document. ZL50110/11/14 Figure 25 - Jitter Transfer Function - Detail 70 Zarlink Semiconductor Inc. Data Sheet ...

Page 71

... Input Voltage High Input Voltage High, 5V tolerant inputs Typical figures are at 25 ° C and are for design aid only, they are not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (V ) unless otherwise stated. SS ZL50110/11/14 Symbol V DD_IO V DD_CORE ...

Page 72

... Note 2: Worst case assumes the maximum number of active contexts and channels, i.e., 128 contexts/1024 channels. Figures are for the ZL50111. For an indication of power consumption by the ZL50110 and ZL50114, please refer to Section 12.0 and choose the appropriate memory configuration and number of contexts. Input Levels ...

Page 73

... TDM Interface Timing - ST-BUS The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device sourcing the data, or Master mode, where the TDM clocks are generated from the ZL50110/11/14. 11.1.1 ST-BUS Slave Clock Mode TDM ST-BUS Slave Timing Specification ...

Page 74

... Channel 127 bit 1 Figure 26 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps Channel 31 Bit 0 TDM_CLKI (2.048 MHz) TDM_CLKI (4.096 MHz) TDM_F0i TDM_STi TDM_STo Figure 27 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps ZL50110/11/14 Channel 127 bit 0 Channel 0 bit 7 t C16IP t FOIS t STIH STIH ...

Page 75

... HiZ to Active TDM_STi Setup Time TDM_STi Hold Time Table 27 - TDM ST-BUS Master Timing Specification Channel 127 Bit 0 TDM_CLKO TDM_F0o t STIH t STIS TDM_STi B0 Ch 127 Bit 0 TDM_STo Figure 28 - TDM Bus Master Mode Timing at 8.192 Mbps ZL50110/11/14 Symbol Min. Typ. t 54.0 61.0 C16OP t 23.0 - C16OH t 23.0 - C16OL t 237 ...

Page 76

... Refer to H.110 Standard from Enterprise Computer Telephony Forum (ECTF) for the source of these numbers. Note 5: The TDM_FRAME signal is centred on the rising edge of TDM_C8. All timing measurements are based on this rising edge point; TDM_FRAME corresponds to pin TDM_F0i. Phase correction ( Φ ) results from DPLL timing corrections. Note 6: ZL50110/11/14 Channel 0 Bit 7 t C2OP t C4OP ...

Page 77

... TDM_C4 Period TDM_C4 High TDM_C4 Low TDM_C16 Period TDM_C16 High TDM_C16 Low TDM_HDS Output Delay TDM_HDS Output Delay TDM_HDS Output to HiZ TDM_HDS Input Setup TDM_HDS Input Hold Table 29 - TDM H-MVIP Timing Specification ZL50110/11/ Bit C8H C8L t C8P ...

Page 78

... Table 30 shows timing for DS3, which would be the most stringent requirement. Parameter TDM_TXCLK Period TDM_TXCLK High TDM_TXCLK Low TDM_RXCLK Period TDM_RXCLK High TDM_RXCLK Low TDM_TXDATA Output Delay TDM_RXDATA Input Setup TDM_RXDATA Input Hold Table 30 - TDM - LIU Structured Transmission/Reception ZL50110/11/14 Symbol Min. Typ. t 200 244 ...

Page 79

... TXCLK period TXCLK high time TXCLK low time TXCLK rise time TXCLK fall time TXCLK rise to TXD[3:0] active delay (TXCLK rising edge) TXCLK to TXEN active delay (TXCLK rising edge) Table 32 - MII Transmit Timing - 100 Mbps ZL50110/11/14 t CTH t CTP CRH t CRP ...

Page 80

... RXDV input setup time (RXCLK rising edge) RXDV input hold time (RXCLK rising edge) RXER input setup time (RXCL edge) RXER input hold time (RXCLK rising edge) Table 33 - MII Receive Timing - 100 Mbps ZL50110/11/14 100 Mbps Symbol Min. Typ ...

Page 81

... RXCLK RXDV RXD[3:0] RXER Figure 34 - MII Receive Timing Diagram ZL50110/11/ DVS ERH t ERS 81 Zarlink Semiconductor Inc. Data Sheet t t CLO CHI t DVH ...

Page 82

... GTXCLK rise time GTXCLK fall time GTXCLK rise to TXD[7:0] active delay GTXCLK rise to TXEN active delay GTXCLK rise to TXER active delay Table 34 - GMII Transmit Timing - 1000 Mbps GTXCLK t EV TXEN t DV TXD[3:0] TXER ZL50110/11/14 1000 Mbps Symbol Min. Typ 2.5 - GCH t 2.5 - GCL ...

Page 83

... RXDV setup time (RXCLK rising edge) RXDV hold time (RXCLK rising edge) RXER setup time (RXCLK rising edge) RXER hold time (RXCLK rising edge) Table 35 - GMII Receive Timing - 1000 Mbps RXCLK RXDV RXD[7:0] RXER ZL50110/11/14 1000 Mbps Symbol Min. Typ ...

Page 84

... RXD[9:0] setup time (RCB0 rising edge) RXD[9:0] hold time (RCB0 rising edge) REFCLK period REFCLK high wide time REFCLK low wide time t GC GTXCLK TXD[9:0] /I/ /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/ Signal_Detect ZL50110/11/14 1000 Mbps Symbol Min. Typ ...

Page 85

... Table 37 - MAC Management Timing Specification Note 1: Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics. Note 2: Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO. M_MDC M_MDIO Figure 39 - Management Interface Timing for Ethernet Port - Read ZL50110/11/ ...

Page 86

... Must be capable of driving TWO separate RAM loads simultaneously. n Phase 1 SCLK RAM_ADDR[19: READ A2 - WRITE RAM_RW A3 - WRITE A4 - READ A5 - READ RAM_BW[7:0] BW1 A6 - WRITE A7 - READ A8 - WRITE RAM_DATA[63:0] RAM_PARITY[7:0] Figure 41 - External RAM Read and Write Timing ZL50110/11/ Symbol Min. Typ RDV RAV RBW ...

Page 87

... MPC8260. See Section 13.2 for details of CTV how to accommodate this during board design. The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of CPU_TA, not at the positive clock edge during the assertion of CPU_TA. ZL50110/11/14 Symbol Min. Typ ...

Page 88

... CPU_TA NOTE: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed. ZL50110/11/ CAH ...

Page 89

... CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed. Note 2: CPU_DREQ0 shown with positive polarity CPU_SDACK1 shown with negative polarity Figure 45 - CPU DMA Write - MPC8260 ZL50110/11/ CWV t ...

Page 90

... Note 4: In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may be relaxed slightly. Note 5: The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3. ZL50110/11/14 Symbol Min. Typ. CLK - ...

Page 91

... JTAG_TRST is an asynchronous signal. The setup time is for test purposes only. Note 2: Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK. Note 3: Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK. ZL50110/11/14 Symbol Min. Typ ...

Page 92

... HIGH JTAG_TCK t TPH t TPSU JTAG_TMS JTAG_TDI Don't Care JTAG_TDO HiZ Figure 46 - JTAG Signal Timing JTAG_TCK JTAG_TRST Figure 47 - JTAG Clock and Reset Timing ZL50110/11/14 LOW t JCP t TPSU t TOPDV t t LOW HIGH t t RST RSTSU 92 Zarlink Semiconductor Inc. Data Sheet t TPH DC t TPZ ...

Page 93

... Power Characteristics The following graph in Figure 48 illustrates typical power consumption figures for the ZL50110/11/14 family. Typical characteristics are at 1.8V core, 3.3V I/O, 25°C and typical processing. Power is plotted against the number of active contexts, which is the dominant factor for power consumption. ZL501x Power Consumption (Typical Conditions ...

Page 94

... AC potential placing guard traces between the signals usually held ground potential. Particular effort should be made to minimise crosstalk from ZL50110/11/14 outputs and ensuring fast rise time to these inputs. ...

Page 95

... The TDM interface has numerous clocking schemes and as a result of this the input clock traces to the ZL50110/11/14 devices should be treated with care. ...

Page 96

... The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be fitted to ensure correct operation of the TA input to the processor recommended that the logic is fitted close to the ZL50110/11/14 and that the clock to the 74LCX74 is derived from the same clock source as that input to the ZL50110/11/14. ...

Page 97

... To generate a pin for pin compatible PCB for all three variants, the following stuffing options may be used as shown in Figure 50. For the ZL50111 variant, resistors R4 and R6 are not populated. For the ZL50110 and ZL50114 variants, resistors R1, R2, R3 and R5 as well as LEDs for M2 and M3 are not populated. ...

Page 98

... Table 43 lists the various components that are used for each variant. Component LED M1 LED M2 LED M3 LED Table 43 - Mx_LINKUP_LED Stuffing Option ZL50110/11/14 ZL50111 √ √ √ - √ - √ √ √ √ 98 Zarlink Semiconductor Inc. Data Sheet ZL50110 √ - √ √ √ ...

Page 99

... IETF PWE3 draft-ietf-l2tpext-l2tp-base • IETF PWE3 draft-ietf-pwe3-cesopsn • IETF PWE3 draft-ietf-pwe3-satop • ITU-T Y.1413 TDM-MPLS Network Interworking • Optional Packet Memory Device - Micron MT55L128L32P1 8 Mb ZBT-SRAM 14.2 Zarlink Standards • MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification ZL50110/11/14 99 Zarlink Semiconductor Inc. Data Sheet ...

Page 100

... MTIE Maximum Time Interval Error MVIP Multi-Vendor Integration Protocol (a TDM bus standard) Optical Carrier 3 - 155.52 Mbps leased line OC3 PDH Plesiochronous Digital Hierarchy PLL Phase Locked Loop PRS Primary Reference Source Packet Receive PRX ZL50110/11/14 100 Zarlink Semiconductor Inc. Data Sheet ...

Page 101

... Standard Telecom Bus, a standard interface for TDM data streams TDL Tapped Delay Line TDM Time Division Multiplexing UDP User Datagram Protocol (RFC 768) UI Unit Interval VLAN Virtual Local Area Network WFQ Weighted Fair Queuing ZBT Zero Bus Turnaround, a type of synchronous SRAM ZL50110/11/14 101 Zarlink Semiconductor Inc. Data Sheet ...

Page 102

Zarlink Semiconductor 2003 All rights reserved ISSUE 213837 ACN DATE 12Dec02 19Aug03 APPRD. Package Code Previous package codes ...

Page 103

For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...