ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 39

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.5
All CPU Interface signals are 5 V tolerant.
All CPU Interface outputs are high impedance while System Reset is LOW.
CPU_DATA[31:0]
CPU_ADDR[23:2]
CPU_CS
CPU_WE
CPU Interface
Signal
OT
I/O
I U
Table 14 - CPU Interface Package Ball Definition
I/
I
I
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
AF14
AD14
AF25
AB19
AD22
AE23
AC20
AF24
AE22
AD21
AA17
AB18
AC19
AD20
AF23
AE21
AF22
AC18
AB13
AC13
AD13
AE13
AF12
AE12
AD12
AC12
AF11
AB12
AE11
AA12
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
39
AA16
AD19
AE20
AB17
AF21
AC17
AE19
AA15
AB16
AD18
AF19
AE18
AD17
AF20
AB15
AF18
AD11
AF10
AC11
AE10
AD10
AB11
AF9
AC10
AE9
AA11
CPU Data Bus. Bi-directional data bus,
synchronously transmitted with
CPU_CLK rising edge.
NOTE: as with all ports in the
ZL50110/11/14 device, CPU_DATA[0] is
the least significant bit (lsb).
CPU Address Bus. Address input from
processor to ZL50110/11/14,
synchronously transmitted with
CPU_CLK rising edge.
NOTE: as with all ports in the
ZL50110/11/14 device, CPU_ADDR[2] is
the least significant bit (lsb).
CPU Chip Select. Synchronous to rising
edge of CPU_CLK and active low. Is
asserted with CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the CPU_DATA
output during a read, including DMA
read.
CPU Write Enable. Synchronously
asserted with respect to CPU_CLK
rising edge, and active low. Used for
CPU writes from the processor to
registers within the ZL50110/11/14.
Asserted one clock cycle after
CPU_TS_ALE.
Description
Data Sheet