ZL50115 ZARLINK [Zarlink Semiconductor Inc], ZL50115 Datasheet - Page 39

• Manufacturer Part Number: ZL50115
• Description: 32, 64 and 128 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.6.2
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001).
4.7
The following unused inputs must be tied low or high as appropriate.
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
IC_GND
IC_VDD_IO
Miscellaneous Inputs
Signal
Signal
JTAG Interface
Table 14 - Miscellaneous Inputs Package Ball Definitions
W11, Y11, Y19, AA19, AB18
L22
I/O
I U
I U
I U
O
I
Y18
V20
U20
AA18
W20
Table 13 - JTAG Interface Package Ball Definition
Package Balls
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
39
Internally connected. Tie to GND.
Internally connected. Tie to VDD_IO.
JTAG Reset. Asynchronous reset. In normal
operation this pin should be pulled low.
JTAG Clock - maximum frequency is
25MHz, typically run at 10 MHz. In normal
operation this pin should be pulled either
high or low.
JTAG test mode select. Synchronous to
JTAG_TCK rising edge. Used by the Test
Access Port controller to set certain test
modes.
JTAG test data input. Synchronous to
JTAG_TCK.
JTAG test data output. Synchronous to
JTAG_TCK.
Description
Description
Data Sheet