ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 19

• Manufacturer Part Number: ZL50232GDC
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.7
The ZL50232 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone
Disable is detected and released.
Although the ZL50232 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50232. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.
7.0
The ZL50232 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 V compliant only.
7.1
The TAP provides access to many test functions of the ZL50232. It consists of four input pins and one output pin.
The following pins are found on the TAP.
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Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations.
The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to V
not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent
section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to
V
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction register
or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge
of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high
impedance state.
DD1
Interrupts
Test Access Port (TAP)
JTAG Support
when it is not driven from an external source.
Zarlink Semiconductor Inc.
ZL50232
19
Data Sheet
DD1
when it is