ZL50233GDC ZARLINK [Zarlink Semiconductor Inc], ZL50233GDC Datasheet

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Features • Independent multiple channels of echo cancellation; from 4 channels of 64ms to 2 channels of 128ms with the ability to mix channels at 128ms or 64ms in any combination • Independent Power Down mode for each group of ...

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ZL50233 • T1/E1/J1 multichannel echo cancellation • Wireless base stations • Echo Canceller pools • DCME, satellite and multiplexer system Description The ZL50233 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 ...

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Data Sheet IC0 V c4i IC0 V IC0 DD1 SS C IC0 IC0 DD1 D NC IC0 V V DD1 IC0 ...

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ZL50233 Pin Description PIN # PIN Name 208-Ball LBGA V A1, A3,A7,A11, A13, SS A15, A16, B2, B6, B8, B12, B14, B15, B16, C3, C5, C7, C9, C11, C12, C13, C14, C16, D4, D8, D10, D12, D13, E3, E4, E14, ...

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Data Sheet Pin Description (continued) PIN # PIN Name 208-Ball LBGA R11 DS R13 CS R5 R/W R7 DTA D0..D7 T2,T4,T6,T8,T9,T11, T13,T15 A0..A10 P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16 ODE B13 Sout A8 Rout B9 Sin B11 Rin B7 B5 F0i A4 C4i ...

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ZL50233 Pin Description (continued) PIN # PIN Name 208-Ball LBGA Fsel H2 PLLVss1 K3 PLLVss2 PLLV K4 DD TMS M2 TDI M1 TDO N1 TCK P1 N2 TRST R3 RESET 1.0 Device Overview The ZL50233 architecture contains 4 echo cancellers ...

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Data Sheet Each echo canceller contains the following main elements (see Figure 4). • Adaptive Filter for estimating the echo channel • Subtractor for cancelling the echo • Double-Talk detector for disabling the filter adaptation during periods of double-talk • ...

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ZL50233 1.2 Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. ...

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Data Sheet 1.4 Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50233 uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower ...

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ZL50233 The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original ...

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Data Sheet interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state. ...

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ZL50233 2.0 Device Configuration The ZL50233 architecture contains 4 echo cancellers divided into 2 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in ...

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Data Sheet Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 2 groups ...

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ZL50233 In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2, ...

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Data Sheet F0i 15.625 sec ST-BUS F0i GCI interface Active Channels Rin/Sin Rout/Sout Note: Refer to Figure 12 and Figure 13 for timing details. Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data ...

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ZL50233 6.0 Memory Mapped Control and Status registers Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a “per channel” basis to monitor and ...

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Data Sheet 6.4 Power Up Sequence On power up, the RESET pin must be held low for 100 s. Forcing the RESET pin low will put the ZL50233 in power down state. In this state, all internal clocks are halted, ...

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ZL50233 After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address mapping of ...

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Data Sheet 7.3 Test Data Registers As specified in IEEE 1149.1, the ZL50233 JTAG Interface contains three test data registers: • Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around ...

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ZL50233 Power-up 02 Bit 7 Bit 6 Reset INJDis Reset When high, the power-up initialization is executed which presets all register bits including this bit and clears the Adaptive Filter coefficients. INJDis When high, the noise injection process is disabled. ...

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Data Sheet Power-up 00 hex Bit 7 Bit 6 Reserve TD DTDet Reserve Reserved bit. TD Logic high indicates the presence of a 2100Hz tone. DTDet Logic high indicates the presence of a double-talk condition. Reserve Reserved bit. Reserve Reserved ...

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ZL50233 Amplitude of MU 1.0 Flat Delay (FD ) 7-0 -16 2 9.0 Functional Description of Register Bits The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) to ...

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Data Sheet Power-up FB hex Bit 7 Bit 6 NLRun2 InjCtrl NLRun1 NLRun2 When high, the comfort noise level estimator actively rejects double-talk as being background noise. When low, the noise level estimator makes no such distinction. InjCtrl Selects which ...

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ZL50233 Power-up 16 hex Bit 7 Bit 6 Bit 5 NS7 NS6 NS5 This register is used to scale the comfort noise up or down. Larger values will increase the relative level of comfort noise. The default value of 16 ...

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Data Sheet Power-up N/A Bit 7 Bit 6 SP15 SP14 SP13 Power-up N/A Bit 7 Bit 6 SP7 SP6 These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in 16-bit ...

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ZL50233 ECA: Double-Talk Detection Threshold Register 2 Power-up 48 hex ECB: Double-Talk Detection Threshold Register 2 Bit 7 Bit 6 Bit 5 DTDT15 DTDT14 DTDT13 ECA: Double-Talk Detection Threshold Register 1 Power-up 00 ECB: Double-Talk Detection Threshold Register 1 hex ...

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Data Sheet ECA: Adaptation Step Size Register 2 (MU) Power-up 40 hex ECB: Adaptation Step Size Register 2 (MU) Bit 7 Bit 6 Bit 5 MU15 MU14 MU13 ECA: Adaptation Step Size Register 1 (MU) Power-up 00 hex ECB: Adaptation ...

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ZL50233 Power-up 00 Bit 7 Bit 6 WR_all ODE MIRQ Write all control bit: When high, Group 0 and 1 Echo Cancellers Registers are mapped into WR_all 0000 to 0003F hex hex Cancellers as per Group 0. When low, address ...

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Data Sheet Main Control Register 1 (EC Group 1) Bit 7 Bit 6 Bit 5 Unused Unused Unused Unused Unused Bits. MTDBI Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. ...

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ZL50233 Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage (V DD1 2 Core Supply Voltage (V 3 Input Voltage 4 Input Voltage on any 5V Tolerant I/O pins 5 Continuous Current at digital outputs 6 Package power dissipation 7 Storage ...

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Data Sheet AC Electrical Characteristics - Voltages are with respect to ground (V ss Characteristics 1 CMOS Threshold 2 CMOS Rise/Fall Threshold Voltage High 3 CMOS Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated ...

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ZL50233 AC Electrical Characteristics Characteristic 1 Master Clock Frequency, - Fsel = 0 - Fsel = 1 2 Master Clock Low 3 Master Clock High † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at ...

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Data Sheet F0i C4i Rout/Sout Rin/Sin F0i C4i Sout/Rout Sin/Rin t FPW FPS FPH t SOD Bit 7, Channel 0 Bit 6, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 ...

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ZL50233 MCLK DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 16 - Motorola Non-Multiplexed Bus Timing 34 t MCH t MCL Figure 15 - Master Clock t CSS t RWS t ADS VALID ADDRESS t DDR VALID ...

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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...