ZL50233GDC ZARLINK [Zarlink Semiconductor Inc], ZL50233GDC Datasheet - Page 19

• Manufacturer Part Number: ZL50233GDC
• Description: 4 Channel Voice Echo Cancellor
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Data Sheet
7.3
As specified in IEEE 1149.1, the ZL50233 JTAG Interface contains three test data registers:
•
•
•
8.0
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the ZL50233 core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
Bypass
AdpDis
INJDis
Reset
Reset
ExtDl
BBM
Bit 7
PAD
Test Data Registers
0
Register Description
When high, the power-up initialization is executed. This presets all register bits including this bit
and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always
set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same
logic value to avoid conflict.
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains register
controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter
coefficients are set to zero and the filter adaptation is stopped. When low, output data on both
Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one 128ms
echo canceller. When low, Echo Cancellers A and B of the same group operate independently.
INJDis
Bit 6
Power-up 00
Echo Canceller A (ECA): Control Register 1
BBM
Bit 5
hex
Functional Description of Register Bits
Zarlink Semiconductor Inc.
Bit 4
PAD
Bypass
Bit 3
R/W Address: 00
AdpDis
Bit 2
hex
+ Base Address
Bit 1
0
ZL50233
ExtDI
Bit 0
19