ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 100

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.10
I²C Address 07A-087, CPU Address:h882-88F
Accessed by CPU and I²C (R/W)
Same as QOSC00, QOSC01
12.3.9.11
Accessed by CPU and I
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Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.12
Accessed by CPU and I²C (R/W)
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Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.13
Accessed by CPU (R/W)
W0 – QOSC28[5:0] – CREDIT_C00 (CPU Address 89C)
W1 – QOSC29[5:0] – CREDIT_C01 (CPU Address 89D)
W2 – QOSC30[5:0] – CREDIT_C02 (CPU Address 89E)
W3 – QOSC31[5:0] – CREDIT_C03 (CPU Address 89F)
QOSC28 through QOSC31 represents one set of WFQ parameters for MMAC port. The granularity of the numbers
is 1, and their sum must be 64. QOSC31 corresponds to W3 that is the highest priority, and QOSC27 corresponds
to W0. Default scheduling method will be strict priority across all queues. Only when the bit 7 in the class is set, the
queue will be scheduled as WFQ. The credit number also works as shaper credit if bit 6 is set. The queue with
QOSC16 – BYTE_L11 Level 1 for queue 1 (I
QOSC17 – BYTE_L21 Level 2 for queue 1 (I
QOSC18 – BYTE_L12 Level 1 for queue 2 (I
QOSC19 – BYTE_L22 Level 2 for queue 2 (I
QOSC20 – BYTE_L13 Level 1 for queue 3 (I
QOSC21 – BYTE_L23 Level 2 for queue 3 (I
QOSC22 – BYTE_L11 Level 1 for queue 1 (I²C Address h08E, CPU Address 896)
QOSC23 – BYTE_L21 Level 2 for queue 1 (I²C Address h08F, CPU Address 897)
QOSC24 – BYTE_L12 Level 1 for queue 2 (CPU Address 898)
QOSC25 – BYTE_L22 Level 2 for queue 2 (CPU Address 899)
QOSC26 – BYTE_L13 Level 1 for queue 3 (CPU Address 89A)
QOSC27 – BYTE_L23 Level 2 for queue 3 (CPU Address 89B)
QOSC16 - QOSC21 - Classes Byte Limit CPU port
QOSC02, QOSC15 - Classes Byte Limit port 1-7
QOSC22 - QOSC27 - Classes Byte Limit MMAC port
QOSC28 - QOSC31 - Classes WFQ Credit For MMAC
2
C (R/W):
Zarlink Semiconductor Inc.
2
2
2
2
2
2
C Address h088, CPU Address 890)
C Address h089, CPU Address 891)
C Address h08A, CPU Address 892)
C Address h08B, CPU Address 893)
C Address h08C, CPU Address 894)
C Address h08D, CPU Address 895)
ZL50400
100
Data Sheet