ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 22

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.0
2.1
Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table
database (MCT), and the Network Management (NM) Database statistics counters and MIB.
The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the
received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the
egress port.
A memory arbiter is used to arbitrary the memory access requests from various sources. A Built In Self Test (BIST)
is used to detect any error in the memory array when the device is powered up. The BIST can also be requested by
the writing to the GCR register.
2.2
2.2.1
The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M),
Reverse MII, or Reverse GPSI (only for 10M).
The RMAC of the ZL50400 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full
Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon
collision for up to 16 total transmissions.
These eight ports are denoted as ports 0 to 7. The PHY addresses for the PHY devices connected to the 8 RMAC
ports has to be from 08h (port 0) to 0Fh (port 7).
Internal Memory
MAC Modules
Block Functionality
RMII MAC Module (RMAC)
Management
Module
M
GMAC
Figure 2 - Functional Block Diagram
Frame Engine
Zarlink Semiconductor Inc.
ZL50400
Internal Memory
22
RMAC X 8
Search Engine
8
Memory Block
Other Internal
Data Sheet