ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 96

• Manufacturer Part Number: ZL50404GDC
• Description: Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.9.4
I²C Address h073, CPU Address 848
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
13.3.9.5
I²C Address h072, CPU Address 849
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x24)
13.3.9.6
I²C Address h0C2+n, CPU Address 860+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
13.3.9.7
I²C Address h0CB, CPU Address 868
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
13.3.9.8
I²C Address h0CA, CPU Address 869
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x12)
13.3.9.9
Accessed by CPU and I²C (R/W)
•
•
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
13.3.9.10
I²C Address 07A-07F, CPU Address:h882-887
Accessed by CPU and I²C (R/W)
Same as QOSC00, QOSC01
QOSC00 – BYTE_L1 (I²C Address h078, CPU Address 880)
QOSC01 – BYTE_L2 (I²C Address h079, CPU Address 881)
PR100_CPU – Port CPU Reservation
PRM – Port MMAC Reservation
PTH100_n – Port 0~3 Threshold
PTH100_CPU – Port CPU Threshold
PTHG – Port MMAC Threshold
QOSC00, QOSC01 - Classes Byte Limit port 0
QOSC02, QOSC07 - Classes Byte Limit port 1-3
Zarlink Semiconductor Inc.
ZL50404
96
Data Sheet