CD4051BCJ National Semiconductor, CD4051BCJ Datasheet

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CD4051BCJ

Manufacturer Part Number
CD4051BCJ
Description
Manufacturer
National Semiconductor
Datasheets

Specifications of CD4051BCJ

Case
DIP-16
Date_code
8652/CB
C 1995 National Semiconductor Corporation
CD4051BM CD4051BC Single 8-Channel Analog
CD4052BM CD4052BC Dual 4-Channel Analog
CD4053BM CD4053BC Triple 2-Channel Analog
General Description
These analog multiplexers demultiplexers are digitally con-
trolled analog switches having low ‘‘ON’’ impedance and
very low ‘‘OFF’’ leakage currents Control of analog signals
up to 15V
3 –15V For example if V
analog signals from
tal inputs of 0–5V The multiplexer circuits dissipate ex-
tremely low quiescent power over the full V
V
state of the control signals When a logical ‘‘1’’ is present at
the inhibit input terminal all channels are ‘‘OFF’’
CD4051BM CD4051BC is a single 8-channel multiplexer
having three binary control inputs A B and C and an inhibit
input The three binary signals select 1 of 8 channels to be
turned ‘‘ON’’ and connect the input to the output
CD4052BM CD4052BC is a differential 4-channel multiplex-
er having two binary control inputs A and B and an inhibit
input The two binary input signals select 1 or 4 pairs of
channels to be turned on and connect the differential ana-
log inputs to the differential outputs
CD4053BM CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs A B and C and
Connection Diagrams
DD
b
Multiplexer Demultiplexer
Multiplexer Demultiplexer
Multiplexer Demultiplexer
V
CD4051BM CD4051BC
EE
p-p
supply voltage ranges independent of the logic
can be achieved by digital signal amplitudes of
b
5V to
DD
e
a
TL F 5662
5V V
5V can be controlled by digi-
SS
Order Number CD4051B CD4052B or CD4053B
e
0V and V
DD
b
EE
CD4052BM CD4052BC
Dual-In-Line Packages
V
eb
SS
and
5V
an inhibit input Each control input selects one of a pair of
channels which are connected in a single-pole double-throw
configuration
Features
Y
Y
Y
Y
Y
Y
Y
Wide range of digital and analog signal levels digital
3– 15V analog to 15V
Low ‘‘ON’’ resistance 80
nal-input range for V
High ‘‘OFF’’ resistance channel leakage of
(typ ) at V
Logic level conversion for digital addressing signals of
3– 15V (V
15 V
Matched switch characteristics
V
Very low quiescent power dissipation under all digital-
control input and supply conditions 1
V
Binary address decoding on chip
DD
DD
b
b
p-p
V
V
EE
SS
(V
DD
DD
DD
e
e
b
b
15V
V
b
DD
V
V
V
SS
EE
EE
b
e
e
V
e
EE
DD
3 – 15V) to switch analog signals to
10V
15V)
p-p
e
b
10V
V
CD4053BM CD4053BC
EE
(typ ) over entire 15V
e
15V
R
RRD-B30M105 Printed in U S A
ON
e
5
October 1989
W (typ ) at
TL F 5662 – 1
(typ ) for
g
p-p
10 pA
sig-

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