GAL16LV8C-10LJ Lattice Semiconductor Corp., GAL16LV8C-10LJ Datasheet

GAL16LV8C-10LJ

Manufacturer Part Number

GAL16LV8C-10LJ

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.GAL16LV8.pdf (22 pages)

2.GAL16LV8C-10LJ.pdf (22 pages)

3.GAL16LV8C-15LJ.pdf (22 pages)

Specifications of GAL16LV8C-10LJ

Case

PLCC/20

Date_code

00+

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• HIGH PERFORMANCE E

• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE

• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)

• E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

The GAL16LV8D, at 3.5 ns maximum propagation delay time,

provides the highest speed performance available in the PLD

market. The GAL16LV8C can interface with both 3.3V and 5V

signal levels. The GAL16LV8 is manufactured using Lattice

Semiconductor's advanced 3.3V E

bines CMOS with Electrically Erasable (E

High speed erase times (<100ms) allow the devices to be repro-

grammed quickly and efficiently.

The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-

tecture as its 5V counterpart and supports all architectural features

such as combinatorial or registered macrocell operations.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

16lv8_05

Features

Description

— 3.5 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 2.5 ns Maximum from Clock Input to Data Output

— UltraMOS

— JEDEC-Compatible 3.3V Interface Standard

— 5V Compatible Inputs

— I/O Interfaces with Standard 5V TTL Devices

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— 100% Functional Testability

— Glue Logic for 3.3V Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

(GAL16LV8C)

Advanced CMOS Technology

CMOS

CMOS process, which com-

TECHNOLOGY

) floating gate technology.

Functional Block Diagram

Pin Configuration

I/CLK

GND

GAL16LV8

Low Voltage E

Top View

I/CLK

PLCC

I/OE

Generic Array Logic™

GAL16LV8

I/O/Q

Vcc

CLK

I/O/Q

OLMC

I/O/Q

CMOS PLD

August 2004

I/O/Q

I/OE

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