CY7C1041B-12ZXC Cypress Semiconductor Corporation., CY7C1041B-12ZXC Datasheet
CY7C1041B-12ZXC
Manufacturer Part Number
CY7C1041B-12ZXC
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY7C1041B-12ZXC
Case
TSOP44
Date_code
2006+
Cypress Semiconductor Corporation
Document #: 38-05142 Rev. *A
Features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
• High speed
• Low active power
• Low CMOS standby power (L version)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
A
A
A
A
A
A
A
A
A
Logic Block Diagram
0
1
2
3
4
5
6
7
8
— t
— 1540 mW (max.)
— 2.75 mW (max.)
AA
= 12 ns
INPUT BUFFER
1024 x 4096
DECODER
COLUMN
256K x 16
ARRAY
•
3901 North First Street
I/O
I/O
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
7
15
•
17
). If Byte High Enable (BHE) is LOW, then data
San Jose
8
256K x 16 Static RAM
through I/O
Pin Configuration
0
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
SS
to I/O
,
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
CA 95134
0
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Top View
through I/O
TSOP II
7
. If Byte High Enable (BHE) is
15
SOJ
0
) is written into the location
through A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Revised March 24, 2005
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
NC
A
A
A
A
A
•
15
CY7C1041B
SS
CC
17
16
15
14
13
12
11
10
) are placed in a
0
15
14
13
12
11
10
9
8
17
through I/O
).
408-943-2600
8
to I/O
15
. See
7
), is
0
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