CY7C1041-25ZC Cypress Semiconductor Corporation., CY7C1041-25ZC Datasheet

CY7C1041-25ZC

Manufacturer Part Number

CY7C1041-25ZC

Description

256K x 16 Static RAM

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1041-25ZC.pdf (10 pages)

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Features

Functional Description

The CY7C1041 is a high-performance CMOS static RAM or-

ganized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O

Selection Guide

Cypress Semiconductor Corporation

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current

(mA)

Shaded areas contain preliminary information.

• High speed

• Low active power

• Low CMOS standby power (L version)

• 2.0V Data Retention (400 W at 2.0V retention)

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

Logic Block Diagram

— t

— 1430 mW (max.)

— 2.75 mW (max.)

= 15 ns

INPUT BUFFER

1024 x 4096

DECODER

COLUMN

256K x 16

ARRAY

Com’l

Ind’l

•

through I/O

3901 North First Street

7C1041-12

280

0.5

), is

I/O

– I/O

BHE

BLE

1041–1

7C1041-15

written into the location specified on the address pins (A

through A

from I/O pins (I/O

specified on the address pins (A

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O

then data from memory will appear on I/O

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The input/output pins (I/O

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY7C1041 is available in a standard 44-pin 400-mil-wide

body width SOJ and 44-pin TSOP II package with center pow-

er and ground (revolutionary) pinout.

260

0.5

•

San Jose

). If Byte High Enable (BHE) is LOW, then data

7C1041-17

256K x 16 Static RAM

to I/O

250

0.5

through I/O

Pin Configuration

I/O

•

. If Byte High Enable (BHE) is LOW,

CA 95134

through I/O

Top View

TSOP II

7C1041-20

SOJ

) is written into the location

through A

230

0.5

BHE

BLE

I/O

CY7C1041

) are placed in a

•

to I/O

1041–2

October 4, 1999

408-943-2600

7C1041-25

220

0.5

. See the

Related parts for CY7C1041-25ZC

CY7C1041-25ZC Summary of contents

Page 1

... TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The CY7C1041 is a high-performance CMOS static RAM or- ganized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable ...

Page 2

... CE > > < MAX , Com’l CC – 0.3V, CC Com’l L > V – 0.3V < 0.3V Ind’ CY7C1041 [1] ................................ –0. Ambient [2] Temperature V CC 0°C to +70°C 5V –40°C to +85°C 7C1041-15 7C1041-17 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0 ...

Page 3

... V > V – 0.3V Ind’ < 0.3V Test Conditions MHz 5. 481 5V 3.0V R2 GND 5 pF 255 INCLUDING JIG AND SCOPE (b) 1041–3 3 CY7C1041 7C1041-20 7C1041-25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 0.5 –0.5 0.8 –0.5 0.8 –1 +1 –1 +1 –1 +1 –1 ...

Page 4

... HZCE LZCE HZOE LZOE HZWE HZWE 4 CY7C1041 7C1041-15 7C1041-17 Min. Max. Min. Max ...

Page 5

... Over the Operating Range [10] Conditions 2.0V > V – 0.3V, CC Com’ > V – 0. CY7C1041 7C1041-25 Max. Min. Max. Unit ...

Page 6

... WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. DATA RETENTION MODE 3.0V V > CDR OHA DOE LZOE DATA VALID 50 CY7C1041 3. 1041–5 DATA VALID 1041-6 t HZOE t HZCE t HZBE HIGH IMPEDANCE ICC CC 50% I ISB SB 1041-7 ...

Page 7

... Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state SCE PWE PWE t SCE CY7C1041 1041 1041-9 ...

Page 8

... Read All Bits High Z Read Lower Bits Only Data Out Read Upper Bits Only Data In Write All Bits High Z Write Lower Bits Only Data In Write Upper Bits Only High Z Selected, Outputs Disabled 8 CY7C1041 LZWE 1041-10 Mode Power Standby (I SB Active (I ...

Page 9

... Speed (ns) Ordering Code 15 CY7C1041-15VC CY7C1041L-15VC CY7C1041-15ZC CY7C1041L-15ZC 17 CY7C1041-17VC CY7C1041L-17VC CY7C1041-17ZC CY7C1041L-17ZC 20 CY7C1041-20VC CY7C1041L-20VC CY7C1041-20ZC CY7C1041L-20ZC 25 CY7C1041-25VC CY7C1041L-25VC CY7C1041-25ZC CY7C1041L-25ZC 15 CY7C1041-15ZI CY7C1041-15VI 17 CY7C1041-17ZI CY7C1041-17VI 20 CY7C1041-20ZI CY7C1041-20VI 25 CY7C1041-25ZI CY7C1041-25VI Document #: 38-00644-B Package Name Package Type V34 44-Lead (400-Mil) Molded SOJ V34 44-Lead (400-Mil) Molded SOJ ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 44-Lead (400-Mil) Molded SOJ V34 44-Pin TSOP II Z44 CY7C1041 51-85082-B 51-85087-A ...

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