K4T1G044QC SAMSUNG [Samsung semiconductor], K4T1G044QC Datasheet - Page 15

• Manufacturer Part Number: K4T1G044QC
• Description: 1Gb C-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

Note :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
5. Definitions for IDD
For purposes of IDD testing, the following parameters are utilized
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) and t FAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 8bank devices x4/ x8
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 4/4/4 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
K4T1G044QC
K4T1G084QC
bits 10 and 11.
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
t RRD(IDD)-x4/x8
t RRD(IDD)-x16
t RASmin(IDD)
Parameter
t RCD(IDD)
t RFC(IDD)
t RC(IDD)
t CK(IDD)
t RP(IDD)
CL(IDD)
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
masks or strobes.
DDR2-800
6-6-6
105
7.5
2.5
15
60
10
45
15
6
15 of 26
DDR2-667
5-5-5
105
7.5
15
60
10
45
15
5
3
DDR2-533
4-4-4
3.75
105
7.5
15
60
10
45
15
4
DDR2-400
DDR2 SDRAM
3-3-3
Rev. 1.1 June 2007
105
7.5
15
55
10
40
15
3
5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns