K4T51043QE SAMSUNG [Samsung semiconductor], K4T51043QE Datasheet - Page 20

• Manufacturer Part Number: K4T51043QE
• Description: 512Mb E-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
K4T51043QE
K4T51083QE
K4T51163QE
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input tIPW
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ sig-
nals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
Symbol
min(tCL,t
tAC min
2* tAC
- 0.25
tQHS
2500
tHP -
- 400
- 350
0.45
0.45
0.35
0.35
min
CH)
125
0.35
min
250
175
0.2
0.2
0.4
0.35
0.9
0.4
7.5
50
0.6
2
x
x
x
DDR2-800
tAC max
tAC max
tAC max
20 of 45
8000
max
0.55
0.55
0.25
200
300
400
350
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
min(tCL,
tAC min
2*tAC
tQHS
3000
tHP -
-0.25
-400
tCH)
0.45
0.45
0.35
0.35
0.35
min
-450
175
100
0.35
275
200
min
0.6
0.2
0.2
0.4
0.9
0.4
7.5
x
2
x
x
DDR2-667
tAC max
tAC max
tAC max 2* tACmin tAC max 2* tACmin
+400
8000
max
0.55
0.55
0.25
+450
240
340
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
min(tCL,
tAC min
tQHS
tHP -
-0.25
3750
0.45
0.45
tCH)
0.35
0.35
min
-500
-450
225
100
0.35
375
250
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
2
x
x
x
DDR2-533
tAC max
tAC max
+500
+450
8000
max
0.55
0.55
0.25
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
min(tCL,
tAC min
tQHS
5000
tHP -
-0.25
tCH)
-600
-500
0.45
0.45
0.35
0.35
0.35
min
275
150
0.35
475
350
0.6
0.2
0.2
0.4
0.9
0.4
7.5
x
2
DDR2 SDRAM
x
x
Rev. 1.8 July 2007
DDR2-400
tAC max
tAC max
tAC max
+600
+500
max
0.55
0.55
8000
0.25
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
Notes
15,16,
15,16,
14,16,
14,16,
20,21
17,20
17,21
18,23
18,22
24
27
27
22
21
19
28
28
12