HYS64V4200GU-10 SIEMENS [Siemens Semiconductor Group], HYS64V4200GU-10 Datasheet

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HYS64V4200GU-10

Manufacturer Part Number
HYS64V4200GU-10
Description
3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
3.3V 4M x 64/72-Bit 1 BANK SDRAM Module
3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
PC66 & PC100 168 pin unbuffered DIMM Modules
Semiconductor Group
168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules
One bank 4M x 64, 4Mx72 and two bank 8M x 64, 8M x 72 organisation
Optimized for byte-write non-parity and ECC applications
JEDEC standard Synchronous DRAMs (SDRAM)
Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
SDRAM Performance:
Programmed Latencies :
Single +3.3V( 0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E
Utilizes 4M x16 SDRAMs in TSOPII-54 packages
4096 refresh cycles every 64 ms
133,35 mm x 29,31 mm x 4,00 mm card size with gold contact pads
for PC main memory applications
f
t
CK
AC
-8B
-10
Product Speed
-8
Clock frequency (max.)
Clock access time
PC100
PC100
PC66
CL
2
2
3
2
PROM
tRCD
2
2
2
100
-8
6
1
1
100
-8B
tRP
6
2
3
2
-10
66
8
HYS64(72)V4200GU
HYS64(72)V8220GU
Units
MHz
ns
8.98

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HYS64V4200GU-10 Summary of contents

Page 1

... One bank 4M x 64, 4Mx72 and two bank organisation • Optimized for byte-write non-parity and ECC applications • JEDEC standard Synchronous DRAMs (SDRAM) • Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification • SDRAM Performance: • f Clock frequency (max.) ...

Page 2

... RAS Row Address Strobe CAS Column Address Strobe WE Read / Write Input CKE0, CKE1 Clock Enable Address Format: Part Number HYS64V4200GU HYS72V4200GU HYS64V8220GU HYS72V8220GU Semiconductor Group Package Descriptions L-DIM-168-31 100 Mhz bank SDRAM module L-DIM-168-31 ...

Page 3

... VSS 120 79 CLK2 121 80 NC 122 81 WP 123 82 SDA 124 83 SCL 125 84 VCC 126 3 HYS64(72)V4200/8220GU SDRAM-Modules Symbol PIN # Symbol VSS 127 VSS DQ32 128 CKE0 DQ33 129 CS3 DQ34 130 DQMB6 DQ35 131 DQMB7 VCC 132 NC DQ36 133 VCC ...

Page 4

... D4 is only used in the x72 ECC version 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length Block Diagram for and bank SDRAM DIMM modules (HYS64V4200GU) Semiconductor Group CS ...

Page 5

... CS CS LDQM DQMB6 DQ0-DQ7 DQ(55:48) UDQM DQMB7 DQ8-DQ15 DQ(63:56 D7, (D8,D9 D7, (D8,D9 D7, (D8,D9 D7, (D8,D9) CLK0 2 SDRAM+15pF CLK1 2 SDRAM+15pF CLK2 2 SDRAM+15pF CLK3 2 SDRAM+15pF 5 HYS64(72)V4200/8220GU SDRAM-Modules CS CS LDQM LDQM DQ0-DQ7 DQ0-DQ7 UDQM UDQM DQ8-DQ15 DQ8-DQ15 LDQM LDQM DQ0-DQ7 DQ0-DQ7 UDQM UDQM DQ8-DQ15 DQ8-DQ15 ...

Page 6

... Input/Output Capacitance Semiconductor Group V = 3.3 V 0.3 V DD, DDQ 0 MHz Symbol ICL HYS64(72)V4200/8220GU SDRAM-Modules Symbol Limit Values min. max. V 2.0 Vcc+ 0 – 0.5 0 2.4 – – 0 – I(L) I – O(L) Limit Values max. ...

Page 7

... C, Vdd = 3.3V 0.3V 1) Symb. ICC1 tck = min. ICC2P tck = Infinity ICC2PS tck = min. ICC2N tck = Infinity ICC2NS CKE>=VIH(min.) ICC3N CKE<=VIL(max.) ICC3P ICC4 ICC5 standard version ICC6 7 HYS64(72)V4200/8220GU SDRAM-Modules -8/-8B -10 Note max. 130 ...

Page 8

... CKSR t 1 – – RCD t 20 – 100k RAS – – RRD t 1 – CCD 8 HYS64(72)V4200/8220GU SDRAM-Modules Limit Values -8B -10 PC100-323 PC66 10 – 10 – 12 – 15 – – 100 – 100 – 83 – 66 – 6 – 8 – 7 – – ...

Page 9

... – 2 – DQZ – DPL – DAL t 0 – 0 DQW 9 HYS64(72)V4200/8220GU SDRAM-Modules Unit -8B -10 PC66 64 – – 10 – – – – 2 CLK – – CLK 2 – ...

Page 10

... These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and -8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. All values are shown per memory component. ...

Page 11

... Minimum Clock Cycle Time Maximum Data Access Time from Clock at CL=1 27 Minimum Row Precharge Time Semiconductor Group HYS64(72)V4200/8220GU 2 PROM - is assembled onto the module. Information about the module 2 PROM device during module production using a serial presence SPD Entry Value 4Mx64 4Mx64 -8 -8B 128 ...

Page 12

... Minimum Row Active to Row Active delay tRRD 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 62-61 Superset information (may be ...

Page 13

... Burst Length supported 17 Number of SDRAM banks 18 Supported CAS Latencies 19 CS Latencies 20 WE Latencies 21 SDRAM DIMM module attributes 22 SDRAM Device Attributes :General 23 Minimum Clock Cycle Time at CAS Latency = 2 24 Maximum data access time from Clock for CL=2 25 Minimum Clock Cycle Time ...

Page 14

... SPD cont’d: Byte# Description 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 32-61 Superset information (may be used in future) ...

Page 15

... L-DIM-168-31 SDRAM DIMM Module package 66, 6,35 2,0 Detail A Semiconductor Group 133,35 127, 42, 124 125 x) x) 6,35 2,0 Detail B 15 HYS64(72)V4200/8220GU SDRAM-Modules 84 1,27 + 0.1 - 168 1,27 1,0 + 0.5 - 0,2 0, Detail C DM168-31.WMF x) on ECC modules only 4,0 ...

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