MC54-74HC259 MOTOROLA [Motorola, Inc], MC54-74HC259 Datasheet

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MC54-74HC259

Manufacturer Part Number
MC54-74HC259
Description
8-Bit Addressable Latch 1-of-8 Decoder
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Addressable Latch
1-of-8 Decoder
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non–addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one–of–eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259 as an addressable
latch, changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the memory
mode.
10/95
Motorola, Inc. 1995
The MC54/74HC259 is identical in pinout to the LS259. The device inputs
The HC259 has four modes of operation as shown in the mode selection
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 202 FETs or 50.5 Equivalent Gates
ADDRESS
INPUTS
ENABLE
DATA IN
RESET
A0
A1
A2
1
2
3
13
15
14
LOGIC DIAGRAM
PIN 16 = V CC
PIN 8 = GND
10
12
11
4
5
6
7
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
1
REV 6
16
16
MC54/74HC259
16
Enable
C
H
H
H
H
L
L
L
L
1
Address Inputs
1
H
H
L
L
LATCH SELECTION TABLE
MODE SELECTION TABLE
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
ORDERING INFORMATION
GND
1
Q0
Q1
Q2
Q3
A0
A1
A2
PIN ASSIGNMENT
B
H
H
H
H
L
L
L
L
Reset
1
2
3
4
5
6
7
8
H
H
L
L
A
H
H
H
H
L
L
L
L
8–Line Demultiplexer
CERAMIC PACKAGE
PLASTIC PACKAGE
Addressable Latch
SOIC PACKAGE
16
15
14
13
12
10
11
CASE 751B–05
CASE 620–10
CASE 648–08
9
N SUFFIX
D SUFFIX
J SUFFIX
Memory
Ceramic
Plastic
SOIC
Mode
Reset
Addressed
V CC
RESET
ENABLE
DATA IN
Q7
Q6
Q5
Q4
Latch
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

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MC54-74HC259 Summary of contents

Page 1

... Addressable Latch 1-of-8 Decoder High–Performance Silicon–Gate CMOS The MC54/74HC259 is identical in pinout to the LS259. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC259 has four modes of operation as shown in the mode selection table ...

Page 2

... MC54/74HC259 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

... MC54/74HC259 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... MC54/74HC259 t r DATA IN 90% 50% 10% t PLH 90% 50% OUTPUT Q 10% t TLH Figure 1. DATA ENABLE 50% 50% t PHL OUTPUT Q Figure 3. DATA IN OR 50% ADDRESS t h(H) SELECT t su ENABLE 50% Figure 5. MOTOROLA SWITCHING WAVEFORMS DATA ADDRESS V CC SELECT GND t PHL t PHL OUTPUT Q t THL V CC ...

Page 5

... DATA INPUT A0 ADDRESS A1 INPUTS A2 14 ENABLE 15 RESET High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM DECODER MC54/74HC259 MOTOROLA ...

Page 6

... MC54/74HC259 –A – –T – SEATING PLANE 0.25 (0.010) M –A – 0.25 (0.010) –A – –T – SEATING PLANE 0.25 (0.010 MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620–10 ISSUE V – ...

Page 7

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MC54/74HC259/D* 7 MC54/74HC259 MC54/74HC259/D MOTOROLA ...

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