EM639165TS-7G Etron Technology Inc., EM639165TS-7G Datasheet

EM639165TS-7G

Manufacturer Part Number

EM639165TS-7G

Description

Manufacturer

Etron Technology Inc.

Datasheet

1.EM639165VM-7G.pdf (59 pages)

Specifications of EM639165TS-7G

Case

TSOP

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Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

EM639165TS-7G

Manufacturer:

ETRON

Quantity:

1 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

EM639165TS-7G

Manufacturer:

ETRONTECH

Quantity:

20 000

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H&T Electronics

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EM639165TS-7G

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Features

• Fast access time from clock: 5.4/5 ns

• Fast clock rate: 143/166MHz

• Fully synchronous operation

• Internal pipelined architecture

• 2M word x 16-bit x 4-bank

• Programmable Mode registers

• Auto Refresh and Self Refresh

• 4096 refresh cycles/64ms

• CKE power down mode

• Single +3.3V power supply

• Interface: LVTTL

• 54-pin 400 mil plastic TSOP II package

• 54-Ball, 8.0 mm x 8.0 mm TFBGA package

- CAS Latency: 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst stop function

- Pb free and Halogen free

- Pb free

Key Specifications

Ordering Information

TS : indicates TSOP II package

VM : indicates TFBGA package

G: indicates Pb and Halogen Free for TSOPII Package

Etron Technology, Inc.

No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.

TEL: (886)-3-5782345

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

Etron Confidential

tRAS Row Active time(min.)

tCK3 Clock Cycle time(min.)

tAC3 Access time from CLK(max.)

EM639165TS/VM-6G

EM639165TS/VM-7G

tRC

indicates Pb Free for TFBGA Package

Part Number

Row Cycle time(min.)

EM639165

FAX: (886)-3-5778671

Frequency

166MHz

143MHz

8M x 16 bit Synchronous DRAM (SDRAM)

Overview

synchronous DRAM containing 128 Mbits. It is internally

configured as 4 Banks of 2M word x 16 DRAM with a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Read and write

accesses to the SDRAM are burst oriented; accesses start

at a selected location and continue for a programmed

number of locations in a programmed sequence.

Accesses begin with the registration of a BankActivate

command which is then followed by a Read or Write

command.

Write burst lengths of 1, 2, 4, 8, or full page, with a burst

termination option. An auto precharge function may be

enabled to provide a self-timed row precharge that is

initiated at the end of the burst sequence. The refresh

functions, either Auto or Self Refresh are easy to use.

can choose the most suitable modes to maximize its

performance.

applications requiring high memory bandwidth and

particularly

applications.

The EM639165 SDRAM is a high-speed CMOS

The EM639165 provides for programmable Read or

By having a programmable mode register, the system

TSOP II, TFBGA

42/42 ns

60/63 ns

Package

5/5.4 ns

6/7 ns

-6/7

well

These

suited

devices

high

(Rev 0.5, Mar./2008)

are

EM639165

performance

well

suited

for

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