INA-12063-TR1 Agilent(Hewlett-Packard), INA-12063-TR1 Datasheet - Page 13

• Manufacturer Part Number: INA-12063-TR1
• Description: 1.5 GHz Low Noise Self-Biased Transistor Amplifier
• Manufacturer: Agilent(Hewlett-Packard)

Before proceeding to the next
step, circuit stability and out-of-
band gain should be re-checked.
Step 7. Designing the Output
Match
The output of the INA-12063 is
normally matched for maximum
power transfer (maximum gain
and lowest output VSWR.)
Maximum power transfer occurs
when the output is matched to
the conjugate of
computed from the same CAD
circuit file as used for determin-
ing
matching network in the previous
step. A typical LNA is matched
for
output.
Note: The small signal match for
maximum power transfer should
not be confused with matching
the output of the INA-12063 for
the highest output power. As
output power is increased, the
device becomes nonlinear
resulting in a shift away from the
pull types of measurements exist
to determine the optimum
impedance match for maximum
output power under nonlinear
conditions, these tests are fairly
tedious and an empirical tuning
approach is often more expedient
to arrive at a solution. The
match may be used as a starting
point in tuning for maximum
output power.
The same comments regarding
single frequency match, high pass
networks, and lumped vs. distrib-
uted elements referred to in the
input matching step above are
applicable to the output matching
circuit.
Once again, out-of-band gain and
stability should be checked.
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match. While various load
opt
ms
in the design of the input
at the input and
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.
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is
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at the
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Step 8. RF Layout
Up to this point, we have com-
pleted the RF electrical design,
the choice of circuit board
material, and the DC circuit. The
next step is to lay out the printed
circuit board. While the layout is
not critical, some precautions
should be considered.
A recommended PCB pad layout
for the miniature SOT-363 (SC-70)
package used by the INA-12063 is
shown in Figure 12 (dimensions
are in inches). This layout pro-
vides ample allowance for pack-
age placement by automated
assembly equipment without
adding parasitics that could impair
the high frequency RF perfor-
mance of the INA-12063. The
layout is shown with a footprint of
a SOT-363 package superimposed
on the PCB pads for reference.
Figure 12. PCB Pad Layout for
INA-12063 Package
(dimensions in inches).
Starting with the package pad
layout in Figure 12, an RF layout
similar to the one in Figure 13 is
suggested as a starting point for
the INA-12063 amplifier.
Figure 13. RF Layout.
0.035
0.026
3
4
6-128
0.016
1
6
0.075
This layout shows the direct
grounding of Pin 5 (the device RF
ground) which should be con-
nected to ground through as short
a path as practical, unless addi-
tional shunt feedback is desired.
Capacitive bypasses should be
placed on the DC connections at
Pins 1 and 4 to prevent possible
feedback and/or oscillation in the
active bias circuit. Multiple vias
are used to ensure good RF
grounding.
It is recommended that the PCB
pads for the two ground pins not
be connected together. Each
ground pin should have its own
separate path to ground, other-
wise, unintentional feedback
could lead to potential instability
in the RF transistor or internal
bias circuit.
Step 9. Final CAD Analysis
and Optimization
Following the completion of the
amplifier electrical design and
layout, it is advisable to do a final
CAD analysis and circuit optimi-
zation. The analysis at this point
will take into account such things
as component parasitics (e.g.,
series L in chip caps), actual
transmission line dimensions and
interconnections, effects of
ground vias, etc.
The circuit should be analyzed
over the full range of the provided
S-parameters to re-verify amplifier
stability and ensure well-behaved
out-of-band performance. With
the full circuit parasitics and
losses taken into account, it may
be necessary to adjust the value
of the shunt stabilizing resistor.
The results of this final analysis
and optimization are then used to
make final adjustments to compo-
nent values and the PCB layout as