M5M4V16169DTP-15 MITSUBISHI [Mitsubishi Electric Semiconductor], M5M4V16169DTP-15 Datasheet

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M5M4V16169DTP-15

Manufacturer Part Number
M5M4V16169DTP-15
Description
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
# 70-pin,400-mil TSOP (type II ) with 0.65mm
# Multiplexed DRAM address inputs for reduced pin
# Selectable output operation (transparent / latched /
# Single 3.3V +/- 0.3V Power Supply.
# 2048 refresh cycles every 64ms (Ad0->Ad10).
# Programmable burst length (1,2,4,8) and burst
# Synchronous design for precise control with
# Output retention by advanced mask clock (CMs#).
# All inputs/outputs low capacitance and LVTTL
# Separate DRAM and SRAM address inputs
# Page Mode capability.
# Auto Refresh capability.
# Self Refresh capability.
lead pitch and 23.49mm package length.
count and higher system densities.
(3.3V +/- 0.15V for -7 part)
sequence (sequential,interleave) with no latency.
compatible.
registered) using set command register cycle.
an external clock (K).
for fast SRAM access.
FEATURES
DESCRIPTION
M5M4V16169TP/RT-8
M5M4V16169TP/RT-10
M5M4V16169TP/RT-15
1.
2.
M5M4V16169TP/RT-7
Preliminary
This document is a preliminary Target Spec. and some of the contents are subject to change without notice.
Type name
The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input
registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word
by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single
monolithic circuit. The block data transfer between the DRAM and the data
transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a
fundamental advantage over a conventional DRAM/SRAM cache.
The RAM is fabricated with a high performance CMOS process, and is ideal for
large-capacity memory systems where high speed, low power dissipation, and
low cost are essential. The use of quadruple-layer polysilicon process combined
with silicide and double layer aluminum wiring technology, a single-transistor
dynamic storage stacked capacitor cell, and a six-transistor static storage cache
cell provide high circuit density at reduced costs.
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI ELECTRIC
Access/cycle
8.0ns/10ns
8.0ns/15ns
5.6ns/7ns
6.4ns/8ns
SRAM
Access/cycle
75ns/120ns
56ns/80ns
49ns/70ns
60ns/90ns
M5M4V16169DTP/RT-7,-8,-10,-15
DRAM
K
CS#
CMd#
RAS#
CAS#
DTD#
Ad
CMs#
CC0#,CC1#
WE#
DQC(u/l)
As
G#
DQ
Vcc
VccQ
Vss
ADF#
MCL
MCH
Dissipation (Typ)
: Master Clock
: Chip Select
: DRAM Clock Mask
: Row Addr. Strobe
: Column Addr. Strobe
: Data Transfer Direction
: DRAM Address
: SRAM Clock Mask
: Control Clocks
: Write Enable
: I/O Byte Control
: SRAM Address
: Output Enable
: Data I/O
: Power Supply
: DQ Power Supply
: Ground
:Address Fetch clock
This pin can be None-Connect.
:Must Connect Low
:Must Connect High
DRAM: 530
SRAM: 860
DRAM: 500
SRAM: 800
DRAM: 430
SRAM: 660
DRAM: 330
SRAM: 420
Power
(REV 1.0) Jul. 1998
DQ15
DQ14
DQ13
VccQ
DQ12
DQ11
VccQ
DQ10
ADF#
DQCu
CMd#
DTD#
CC1#
CC0#
CMs#
RAS#
CAS#
Ad11
Ad10
VddQ
DQCl
VccQ
DQ9
DQ8
MCH
WE#
MCL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Ad9
Ad8
Ad7
Vcc
Ad6
Ad5
Ad4
Ad3
CS#
Vss
As9
As8
As7
As6
Vss
Vss
As5
As4
As3
Vss
Ad0
Ad1
Ad2
As0
As1
As2
Vcc
Vss
Vss
Vss
Vcc
G#
K
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
1
2
3
4
5
6
7
8
9
MITSUBISHI LSIs
Package code:70P3S-M
PINCONFIGURATION
Package code:70P3S-L
(TOP VIEW)
0.65mm
0.65mm
400 mil
400 mil
Type II
Type II
TSOP
TSOP
70Pin
70Pin
Lead
Pitch
Lead
Pitch
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
8
9
7
Ad11
Ad10
As8
As7
As6
DQ15
Vss
DQ14
DQ13
VccQ
DQ12
Vcc
DQ11
VccQ
DQ10
DQ9
Vss
DQ8
MCH
G#
As5
As4
As3
Ad6
Ad5
Ad4
Ad3
ADF#
Vss
Vss
Ad9
Ad8
Ad7
As9
K
CS#
DQ0
Vss
DQ1
DQ2
DQ3
Vss
DQ4
DQ5
DQ6
Vss
DQ7
As0
As1
As2
CC1#
CC0#
CMs#
MCL
RAS#
CAS#
DTD#
Ad0
Ad1
Ad2
1
Vcc
DQCl
DQCu
WE#
CMd#
Vcc
VccQ
VccQ

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