HY5DU561622ETP-28 HYNIX [Hynix Semiconductor], HY5DU561622ETP-28 Datasheet
HY5DU561622ETP-28
Related parts for HY5DU561622ETP-28
HY5DU561622ETP-28 Summary of contents
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... HY5DU561622ETP 256M(16Mx16) gDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Oct. 2005 HY5DU561622ETP 1 ...
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... VDD/VDDQ, tDPL, tDAL change & CL5 insert 0.3 tRCDWT Change (2clk -> 3clk) at 275/ 300/ 350MHz Speed bin 1.0 Changed IDD3P value & Delete 166MHz speed bin 1.1 Rev. 1.1 / Oct. 2005 History 1HY5DU561622ETP Draft Date Remark Oct. 2004 Apr. 2005 Jul. 2005 Sep. 2005 Oct. 2005 ...
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... Source synchronous - data transaction aligned to bidirectional data strobe (DQS) • x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O ORDERING INFORMATION Part No. Power Supply HY5DU561622ETP-28 VDDQ=2.8V HY5DU561622ETP-33 VDDQ=2.6V HY5DU561622ETP-36 HY5DU561622ETP-4 VDDQ=2.5V HY5DU561622ETP-5 Note) Hynix supports Pb free parts for each speed grade with same specification, except Lead free material. ...
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... Pin Pitch ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh 1HY5DU561622ETP DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 DQ9 ...
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... Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. 1HY5DU561622ETP 5 ...
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... Write Data Register 2-bit Prefetch Unit Bank 4Mx16/Bank0 Control 4Mx16 /Bank1 4Mx16 /Bank2 4Mx16 /Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK, DLL /CLK Block Mode Register 1HY5DU561622ETP LDQS,UDQS Data Strobe CLK_DLL Transmitter Data Strobe DS Receiver DS DQ[0:15] 6 ...
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... 1HY5DU561622ETP A10/ CAS WE ADDR code code ...
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... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 1.1 / Oct. 2005 CKEn /CS, /RAS, /CAS, / 1HY5DU561622ETP A10/ LDM UDM ADDR ...
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... OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP 1HY5DU561622ETP Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU561622ETP Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP 1HY5DU561622ETP Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL ...
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... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU561622ETP Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...
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... 1HY5DU561622ETP /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED 1HY5DU561622ETP SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 1.1 / Oct. 2005 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ 1HY5DU561622ETP < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command 1HY5DU561622ETP AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... Yes CAS Latency Reserved Reserved Reserved Reserved Reserved 1HY5DU561622ETP Burst Length Burst Length Sequential Reserved Reserved Reserved 1 ...
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... Interleave ...
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... The HY5DU561622CT supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/ or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength. Rev. 1.1 / Oct. 2005 1HY5DU561622ETP 19 ...
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... RFU* BA0 MRS Type 0 MRS 1 EMRS * All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 1.1 / Oct. 2005 1HY5DU561622ETP RFU* DS DLL A0 DLL enable 0 Enable 1 Diable A6 A1 Output Driver Impedance Control ...
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... DDQ ± the dc value. (TA=0 to 70oC, Voltage referenced to V Symbol Min 0. 0V 1HY5DU561622ETP Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.5 2.625 V 2.6 2.7 V 2.8 2 ...
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... Auto Refresh I tRC=tRFC(min); All banks active DD5 Current Self Refresh CKE=<0.2V; External clock on; I DD6 Current tCK=tCK(min) Rev. 1.1 / Oct. 2005 o (TA Voltage referenced to V Test Condition 1HY5DU561622ETP = 0V) SS Speed 180 180 170 160 150 ...
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... C, Voltage referenced to V Symbol Min 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V 1HY5DU561622ETP = 0V) SS Max Unit 0.35 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...
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... DRL DAL 2.8 7 0.45 0. 0.45 0. -0.7 0 -0.7 0.7 DQSCK t - 0.4 DQSQ t HPmin QHS t CH min t - 0.4 QHS 0.4 0.6 DQSH t 0.4 0.6 DQSL t 0.85 1.15 DQSS 0 1HY5DU561622ETP 33 36 Min Max Min Max 70K 40 70K 3.3 7.0 3.6 7.0 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 -0 ...
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... Rev. 1.1 / Oct. 2005 28 Symbol Min Max 0 0.9 1.1 RPRE t 0.4 0.6 RPST WPRES t 1.5 - WPREH t 0.4 0.6 WPST MRD t 200 - XSC 1tCK t - PDEX + tIS 2tCK tPDEX_RD - + tIS t - 7.8 REFI 1HY5DU561622ETP 33 36 Min Max Min Max 0.4 - 0.4 - 0.9 1.1 0.9 1.1 0.4 0.6 0.4 0 1.5 - 1.5 - 0.4 0.6 0.4 0 200 - 200 - 1tCK 1tCK - - + tIS + tIS 2tCK 2tCK - - + tIS ...
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... CCD DPL t 2 DRL Precharge t 9 DAL -0.7 DQSCK t - DQSQ t HPmin QHS t CH min t - QHS 0.4 DQSH t 0.4 DQSL t 0.85 DQSS t 0.4 DS 1HY5DU561622ETP 4 5 Max Min Max - 70K 40 70K - 7 5.0 7.0 0.55 0.45 0.55 0.55 0.45 0.55 0.7 -0.7 0.7 0.7 -0.7 0.7 0.4 - 0.45 t HPmin - - ...
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... Rev. 1.1 / Oct. 2005 4 Symbol Min Max t 0 0.9 1.1 RPRE t 0.4 0.6 RPST WPRES t 1.5 - WPREH t 0.4 0.6 WPST MRD t 200 - XSC 1tCK t - PDEX + tIS 2tCK tPDEX_RD - + tIS t - 7.8 REFI 1HY5DU561622ETP 5 Unit Note Min Max 0 0.9 1.1 CK 0 0.4 0 200 - CK 4 1tCK - CK + tIS 2tCK - CK + tIS - 7 ...
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... Rev. 1.1 / Oct. 2005 tRC_APCG tRFC tRAS (AUTO Precharge 40ns 19 22 40ns 18 20 40ns 17 18 40ns 14 14 40ns 1HY5DU561622ETP tRCDRD tRCDWT tRP tDAL Unit tCK tCK ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 1.1 / Oct. 2005 Pin CK, CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50 Ω Zo=50 Ω V REF C =30pF L 1HY5DU561622ETP Symbol Min Max Unit C 2.0 3 2.0 3 4.0 5 ...
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... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 1.1 / Oct. 2005 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 1HY5DU561622ETP Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) ...