AX88140AP ETC, AX88140AP Datasheet - Page 22

• Manufacturer Part Number: AX88140AP
• Description: Fast Ethernet MAC Controller
• Manufacturer: ETC

1. The register is used to point the AX88140A to the start of receive descriptors list.
2. The descriptor list resides in physical memory space and must be longword aligned. The
3. Writing to REG3 is permitted only when receive process is in the stopped state. That is, the
1. The register is used to point the AX88140A to the start of transmit descriptors list.
2. The descriptor list resides in physical memory space and must be long-word aligned. The
3. Writing to REG4 is permitted only when transmit process is in the stopped state. That is, the
REG3 Receive List Base Address Register Description
4.2.3 Receive Poll Demand (REG2)
4.2.4 Receive List Base Address (REG3)
4.2.5 Transmit List Base Address (REG4)
FIELD
FIELD
FIELD
AX88140A behaves UNPREDICTABLY when the list are not longword aligned.
REG3 must be written before the receive START command is given .
AX88140A behaves UNPREDICTABLY when the list are not long-word aligned.
REG4 must be written before the transmit START command is given .
31:0
31:2
31:2
1:0
1:0
AX88140A
R/W/C
R/W/C
R/W/C
R/W
R/W
R/W
R/W
W
Tab - 19 REG4 Transmit List Base Address Register Description
Tab - 18 REG3 Receive List Base Address Register Description
Tab - 17 REG2 Receive Poll Demand Register Description
RPD - Receive Poll Demand
When written with any value, the AX88140A checks for receive descriptors to be required. If no
descriptor is available, the receive process returns to the suspended states and REG5<7> is not
asserted. If the descriptor is available the receive process resumes.
Start of receive list
Must be 00 for longword alignment
Start of transmit list
Must be 00 for long-word alignment
DESCRIPTION
22
DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION
PRELIMINARY