EM65100AGH EMC [ELAN Microelectronics Corp], EM65100AGH Datasheet
EM65100AGH
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EM65100AGH Summary of contents
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Elan Microelectronics Crop. EM65100 69COM/ 101SEG 4 Gray Level STN LCD Driver March 08, 2005 Version 0.6 ...
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EM65100 Specification Revision History Version 0.1 Initial version Page 12:Power circuit block diagram Page 16:Parallel input order Page 16,51:delete slave mode Page 18,60:First step to read the specific register Page 21:RAM address of Monochrome mode 0.2 Page 38: bank number ...
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GENERAL DESCRIPTION ................................................................................................................................................. 4 2. FEATURE ............................................................................................................................................................................... 4 3. APPLICATIONS .................................................................................................................................................................... 4 4. PIN CONFIGURATIONS (PACKAGE) ............................................................................................................................. 5 5. FUNCTIONAL BLOCK DIAGRAM ................................................................................................................................ 10 6. PIN DESCRIPTION ............................................................................................................................................................ 12 7. FUNCTIONAL DESCRIPTION ........................................................................................................................................ 16 8. CONTROL REGISTER ...................................................................................................................................................... 41 ...
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... Gold bumped chip Note: The EM65100 series has the following sub-codes depending on their shapes. H: Bare chip (Aluminum pad without bumped); GH: Gold bumped chip; F: COF package; T: TAB (TCP) package Example EM65100AGH 3. Applications Mobile phone Small PDA * This specification is subject to be changed without notice. ...
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... Note: With the Elan logo in down left the pin the down left corner Mark Coordinate (X,Y) U-Left -3195.0,350.0 D-Left -3195.0,-350.0 U-Left and D-Right: * This specification is subject to be changed without notice. 69 COM/ 101 SEG 4 Gray Level STN LCD Driver EM65100AGH Figure 1. Pin configuration Mark U-Right D-Right D-Left and U-Right: 100um 100um EM65100 117 ...
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Pad configuration Item Chip size 95,96,267,268 97~115,248~266 Bump Size Pad Pitch Die thickness (excluding bumps) Bump Height Minimum Bump Gap Coordinate Origin Recommended COG ITO Traces Resistor Interface V0~V4 CAP1+,CAP1-,CAP2+,CAP2-,CAP3+,Vcc VDD,Vci VSSL,VSSH WRB,RDB,CSB,…,D0~D7 RESB * This specification is subject to ...
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PAD Coordinates Table Pin NO Pad Name 1 WRB 2 RESB CSB 5 RDB VSS CKS 17 ...
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Pin NO Pad Name 101 COM29 102 COM28 103 COM27 104 COM26 105 COM25 106 COM24 107 COM23 108 COM22 109 COM21 110 COM20 111 COM19 112 COM18 113 COM17 114 COM16 115 COM15 116 COM14 117 COM13 118 COM12 ...
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Pin NO Pad Name 201 SEG69 202 SEG70 203 SEG71 204 SEG72 205 SEG73 206 SEG74 207 SEG75 208 SEG76 209 SEG77 210 SEG78 211 SEG79 212 SEG80 213 SEG81 214 SEG82 215 SEG83 216 SEG84 217 SEG85 218 SEG86 ...
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Functional block diagram 5.1 System Block Diagram VDD VSS (VSSH,VSSL) CAP1- CAP1+ CAP2- CAP2+ CAP3+ Vcc Vci VREF D1/SDA D0/SCL * This specification is subject to be changed ...
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Power Circuit Block Diagram Vci Booster Circuit VREG AMP VREF + - Rb Ra Booster step set Register * This specification is subject to be changed without notice. 69 COM/ 101 SEG 4 Gray Level STN LCD Driver Vcc ...
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Pin Description 6.1 Power Supply Pins Symbol I/O Power VDD Power supply pin for logic circuit to +1.8 to 3.3V Supply Power VSSL Ground pin for logic circuit, connect to 0V Supply Power VSSH Ground pin for high voltage ...
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System Bus Pins Symbol I/O Reset input pin. RESB I When RESB is “L”, initialization is executed. Data bus / Signal interface related pins. When parallel interface is selected (P/S = “H”), The D7-D0 are 8-bits bi-directional data bus, ...
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LCD Drive Circuit Signals Symbol I/O Segment output pins for LCD drives. According to the data of the Display RAM data, non-lighted at “0”, lighted at “1” (Normal Mode). non-lighted at “1”, lighted at “0” (Reverse Mode) and, by ...
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Oscillating Circuit Pin Symbol I/O Display timing clock source select input pin. CKS I CKS = “H”: Use external clock from CK pin. CKS = “L”: Use internal oscillated clock External clock input pin for display timing. ...
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Functional Description 7.1 MPU Interface 7.1.1 Selection of Interface Type The EM65100 transfers data through 8-bit parallel I/O (D7-D0) or serial data input (SDA, SCL). The parallel interface or serial interface can select by state of P/S pin. When ...
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When serial interface is used, access is only made for 8-bit data transfer. CSB RS SDA D7 D6 SCL 1 2 7.2 Data write to Display RAM and Control Register The data write to display RAM and Control Register use ...
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Read display RAM operation W RB D0~D7 n Address set (AX,AY) Address = n RDB RS The EM65100 can be read the control registers, in case of control register read operation, data bus upper nibble (D3-D0) use for register address ...
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In Gradation Display Mode (MON=”0”) 8-bits bus size access 0H 1H ----------------------------------------------------------------- 18H 19H 0H 8bit 8bit Y-address 44H 8bit 8bit The addresses, X Address and Y Address are possible to be set up so that they can increment automatically ...
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Relationship between Display RAM and Address The Display RAM block diagram shows in the figure below: Bit-order reverse Internal Data Bus W rite:depend on REF Read:depend on Bit order reverse REF W rite Data X-Address (00H~19H) MPU I/F The ...
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Monochrome mode, 8-bits Access mode X Address REF=1 X =0CH REF 00H Note ----- ...
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REF =0 X Address X = 00H ----- 00H 01H ...
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Display Data Structure and Gradation Control For the purpose of gradation control, one pixel requires multiple bits of display RAM. The EM65100 has 2-bit data per output to achieve the gradation display. The EM65100 is connected to an STN ...
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REF=0 SEGi palette LSB Note : Internal X address : nH REF=1 SEGi+3 palette LSB This specification is subject to be ...
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Gradation Palette The EM65100 has two gradation display modes, the gradation fixed display mode and the gradation variable display mode. Select either of the two modes using the gradation display mode register. PWM = “0”: Selects the variable display ...
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Gradation level table (PWM = “1”, fixed mode) (MSB) RAM data (LSB 7.11 Display Timing Circuit The display timing circuit generates internal signals and timing pulses (internal LP, FLM clock. ...
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Output Timing of LCD Driver Display timing at Normal mode (not reverse mode), 1/69 DUTY, and on monochrome mode LP(internal) FLM(internal) M(internal) COM0 COM1 SEG0 SEG1 7.16 LCD Drive Circuit This drive circuit generates four ...
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When in the master operation mode and external clock is used, feed the clock to CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of CR oscillator is programmable. If change this ratio, also ...
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When use built-in booster circuit, output voltage (Vcc) must less than recommended operating voltage (12.0 Volt). If output voltage (Vcc) over recommended operating voltage, correct work of chip can not guarantee. Vcc=9 V Vci=3V VSS=0V 3 times boostng 7.20 Electronic ...
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VDD VDD Vci VREF CAP1- CAP1+ CAP2- CAP2+ CAP3+ Vcc External V2 Power V2 Supply When using external power supply. Recommended value. C1 1.0 to 4.7 μ 1.0 to 2.2 ...
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VDD VDD Vci VREF CAP1- C1 CAP1+ CAP2- C1 CAP2+ C1 CAP3+ C1 Vcc vss vss When using internal power circuit with external reference voltage input. (4 times boosting) Recommended ...
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VDD VDD Vci VREF CAP1- CAP1+ CAP2- CAP2+ CAP3+ External Power Vcc Supply vss When using internal power circuit. (Vcc supplied from external, no use boosting circuit) Recommended value. C2 ...
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Partial Display Function The EM65100 has the partial display function, which can display a part of graphic display area. This function is used be set lower bias ratio, lower boost step, and lower LCD drive voltage. Since setting partial ...
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Select a display duty ratio for the partial display from 1/10, 1/18, 1/26, 1/34, 1/42, 1/50 and 1/58 using the DS(LCD duty ratio) register. Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic volume, the ...
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Precaution when Power ON and Power OFF This LSI may be permanently damaged by high current that may flow if a voltage is supplied to the LCD driver power supply while the system power supply is floating. The detail ...
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VDD,Vci Item Recommended rising time tr Note: The rising time is the time from 10% of VDD, VEE to 90%. 7.27 Example of Setting Registers (1) Initialization * Electrical volume set * Bias Ratio set * Setting power control (DCON= ...
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Display data * Setting display start address * Setting address increment control * Setting X address * Setting Y address * W rite dsiplay data * Setting display on/off control (ON/OFF= "1") (3) Power OFF * Setting HALT= "1" ...
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PROGRAM EXAMPLES Use Elan Risc ΙΙ MCU assembly ;***************************************************************************** ; INITIALIZATION SETTING EXAMPLE OF EM65100 ;***************************************************************************** WRITEOR macro REGSEL,INSDAT ; Write macro MOV A,INSDAT OR A,REGSEL CALL WRITE_LCD_1BYTE endm EM65100_INI: WRITEOR #REREGISTERSET,#0b00000000 WRITEOR #POWERCONTROL,#0b00000001 ; MOV A,#50 CALL WAIT_A_MS WRITEOR ...
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WRITE DISPLAY_PICTURE DATA INTO DISPLAY DATA RAM OF EM65100 ;***************************************************************************** DATA_WRITE_65100: BS REG_PORTB,RS WRITEOR #XADDRESSLOWER,#0b00000000 WRITEOR #XADDRESSUPPER,#0b00000000 WRITEOR #YADDRESSLOWER,#0b00000000 WRITEOR #YADDRESSUPPER,#0b00000000 MOV A,#LINE_Y_MAX MOV DRAMY,A DATA_W1: MOV A,#LINE_X_MAX MOV DRAMX,A BC REG_PORTB,RS DATA_W2: TBRD 01,REG_ACC CALL WRITE_LCD_1BYTE DEC ...
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READ ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES) ; ;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_1BYTE: BC PORTB,CSB1 ;SET CSB LOW BC PORTB,RDB ;SET /RD=0 READ ENABLE MOV A,PORTC ;MOVE ...
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Control Register 8.1 control register Control Register Table (Bank 0) Pins (for 80-family) & Bank Control Register CSB RS WRB ROB RE2 RE1 RE0 Display Data write Display Data read 0 ...
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Control Register Table (Bank 1) Pins (for 80-family) & Bank Control Register CSB RS WRB ROB RE2 RE1 RE0 Gray Mode--White 1stFR [0H Gray Mode--White 2ndFR [1H Gray Mode--White ...
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Control Register Table (Bank 2) Pins (for 80-family) & Bank Control Register CSB RS WRB ROB RE2 RE1 RE0 Gray Mode--Black 3rdFR [0H Gray Mode--Black 4ndFR [1H Display start ...
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Functions of Control Registers The EM65100 has many control registers. In case of control register access, upper nibble of data bus (D7~D4) represent register address, lower nibble of data bus (D3~D0) represent data. The access example is shown in ...
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X Address Register Set AX3 AX2 (At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H ...
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LA6 LA5 LA4 LA3 LA2 ： ： 8.2.7 n Line Alternated Register Set ...
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NLIN=”1” 1st Line 2nd Line LP M 8.2.8 Display Control (1) Register Set SHIF MON (At the tine of reset: {SHIFT, MON, ALLON, ON/OFF}=0H, read address: 8H) Various ...
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Display Control (2) Register REV NLIN (At the tine of reset: {REV, NLIN, REF}=0H, read address: 9H) ※ Mark shows “Don’t care” Various control of display is set up. ...
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After the increment control register has been set. be sure to assign address to the X and Y address registers starting from the lowest bit. Because it is not assuring the data of X and Y address register after setting ...
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In each operation mode, the following increment operation is performed: (i) When gradation display mode and 8-bit access are selected: Address are incremented as described above. (ii) When monochrome display mode and 8-bit access are selected: In the monochrome display ...
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The internal condition at power saving are as follows. (a) The oscillating circuit and power supply circuit are stopped. (b) The LCD drive is stopped, and output of the segment driver and common driver are VSS level. (c) The clock ...
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The booster steps set to VU register VU1 VU0 Booster Operation 0 0 Booster disable (No operation times voltage output times voltage output times voltage output 8.2.14 Bias Setting Register Set ...
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WB3 WB2 WB1 (Read address: 1H) (At the time of reset:WB3~WB0 = “0000” WC3 WC2 WC1 (Read address: 2H) (At ...
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Gray Mode--Dark gray DA3 DA2 (Read address: 8H) (At the time of reset: DA3~DA0 = “1010” DB3 DB2 (Read address: ...
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BD3 BD2 (Read address: 1H) (At the time of reset: BD3~BD0 = “1111”) Set Gray Scale Mode RAM Data[2n:2n+1] are used to specify the four gray level’s pulse width RAM ...
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Display Start Common Set ※ SC2 (At the time of reset:{ SC2,SC1,SC0}=0H, read address: 6H) ※ Mark shows “Don’t care” The SC register set up the scanning start output ...
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Drive waveform when (SPC1, SPC0) =(1, 0) VDD level SCOM VDD level SSEG 1 frame Drive waveform when (SPC1, SPC0) =(1, 1) VDD level SCOM SSEG VSS level 1 frame 8.2.19 Display Select Control ...
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Electronic Volume Register Set DV3 DV2 (Read address: AH ※ DV6 (Read address: BH) (At the time of reset: ...
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The RA register set to specify the address for register read operation. The EM65100 has many registers and has register bank. Therefore need 4-steps to read to read the specific register in maximum case. (1) Write 02H to ...
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The HPM register is the power control for the power supply circuit for liquid crystal drive. HPM = “H”: High power mode HPM = “L”: Normal mode BF1~BF0: The operating frequency in the booster is selected. When the boosting frequency ...
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Relationship between Setting and Common/Display RAM The relationship between the COM pin numbers and the addresses in the Y-direction on the display RAM changes according to the SHIFT command. LCD Duty Set command. Display Starting Common Position Set command, ...
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Absolute maximum ratings 10.1 Absolute maximum ratings Item Symbol Condition Supply voltage (1) VDD Supply voltage (2) Vci Supply voltage (3) Vcc Supply voltage (4) V0 Supply voltage (5) V1,V2,V3,V4 Input voltage VI Storage Tstg temperature ※ 1: D0~D7, ...
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DC characteristics VSS=0V , VDD = 1.8~3. -30 ~85 ℃ Item Symbol High level input VIH voltage Low level input VIL voltage High level output IOH1 VOH = VDD-0.4V current Low level output IOL1 VOL= 0.4V ...
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Relationship of oscillating frequency (fosc) and external clock frequency (fCK) to LCD frame frequency (fFLM) is each display mode Original Display mode oscillating 1/69, 1/58, 1/50 1/42, 1/34, 1/26 clock When use Variable fosc/(2*15*D) built-in gradation oscillating Simple fosc/(2*3*D) circuit ...
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C1=C2=1.0µF, DCON=AMPON=”1” ※ 14 VDD, Vci pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 4 times is used the electronic control is preset (The ...
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AC characteristic (1) 80-family MCU write timing CSB D0-D7 VSS=0V, VDD = 2.7~3. -30~+85 ℃ Item Symbol Address hold time tAH8 Address setup time tAS8 System cycle time in write tCYCWR8 Write pulse ...
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MCU read timing CSB RS RDB D0-D7 VSS=0V , VDD = 2.7~3. -30~+85 ℃ Item Symbol Address hold time tAH8 Address setup time tAS8 System cycle time in read tCYCRD8 Read pulse “L” width tRDLW8 ...
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MCU write timing CSB RS R RB) E (RDB) D0-D7 VSS=0V , VDD = 2.7 ~3. -30~+85 ℃ Item Symbol Address hold time tAH6 Address setup time tAS6 System cycle time in write ...
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MCU read timing CSB RS R RB) E (RDB) D0-D7 VSS=0V , VDD = 2.7~3. -30~+85 ℃ Item Symbol Address hold time tAH6 Address setup time tAS6 System cycle time in write tCYCRD6 ...
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Serial interface timing diagram t CSS CSB RS SCL D0-D7 VSS=0V , VDD = 2.7~3. -30~+85 ℃ Item Symbol Serial clock period tCYCS SCL pulse “H” width tSHW SCL pulse “L” width tSLW Address setup time ...
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Display control timing CLK(internal) t DLP LP(internal) FLM(internal) M(internal) output timing VSS=0V , VDD = 2.4~3. -30~+85 ℃ Item Symbol LP delay time tDLP FLM delay time tDFLM CL = delay time tDM output ...
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Master clock input timing CK VSS=0V , VDD = 2.4~3. -30~+85 ℃ Item Symbol CK pulse “H” width (1) tCKHW1 CK pulse “L” width (1) tCKLW1 CK pulse “H” width (2) tTCKHW2 CK pulse “L” width ...
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Reset timing RESB internal state VSS=0V, VDD = 2.4~3.3V -30~+85 ℃ Item Symbol Reset time tR Reset pulse “L” width tRW VSS=0V, VDD = 1.8~2.4V -30~+85 ℃ Item Symbol Reset time tR Reset pulse “L” ...
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Application circuit (1) Connection to 80-family MCU VCC /IORQ /RES G ND (2) Connection to 68-family MCU VCC A1 to A15 VMA /RES This specification is subject ...
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Connection to the MCU with serial interface VCC PORT1 PORT2 /RES This specification is subject to be changed without notice. 69 COM/ 101 SEG 4 Gray Level STN LCD Driver A0 RS CSB ...