M12L16161A-5T ESMT [Elite Semiconductor Memory Technology Inc.], M12L16161A-5T Datasheet - Page 10

• Manufacturer Part Number: M12L16161A-5T
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

SIMPLIFIED TRUTH TABLE
Note:1 OP Code: Operation Code
Elite Semiconductor Memory Technology Inc.
Bank Active & Row Addr.
Register
Refresh
Read &
Column Address Auto Precharge Enable
Write & Column
Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA: Bank select address.
5.During burst read or write with auto precharge, new read/write command can not be issued.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
A0~ A10/AP, BA: Program keys.(@MRS)
A new command can be issued after 2 clock cycle of MRS.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks precharge state.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
COMMAND
Mode Register Set
Auto Refresh
Self Refresh
Auto Precharge Disable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
Entry
Exit
CKEn-1 CKEn CS
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
X
X
X
X
X
X
X
H
L
H
L
H
L
H
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
t
RP
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
after the end of burst.
P.10
RAS CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
X
X
X
V
X
X
X
V
X
L
L
H
H
L
L
H
H
H
H
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
Publication Date : Jan. 2000
DQM BA A10/AP A9~A0 Note
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
V
V
V
X
M12L16161A
OP CODE
Row Address
Revision : 1.3u
H
H
H
L
L
L
X
X
X
X
X
X
X
(A0~A7)
(A0~A7)
Column
Address
Column
Address
X
1,2
4,5
4,5
3
3
3
3
4
4
6
4
4
7