M12L16161A-5T ESMT [Elite Semiconductor Memory Technology Inc.], M12L16161A-5T Datasheet - Page 16

• Manufacturer Part Number: M12L16161A-5T
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

Page Read Cycle at Different Bank @ Burst Length=4
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.
Elite Semiconductor Memory Technology Inc.
DQ
A10/AP
CLOCK
ADDR
DQM
CL=2
CL=3
CKE
RAS
CAS
WE
CS
BA
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
*Note1
0
Row Active
(A-Bank)
RAa
RAa
1
2
(A-Bank)
CAa
Read
3
Row Active
(B-Bank)
RBb
RBb
4
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
5
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
6
(B-Bank)
CBb
Read
7
8
9
HIGH
P.16
10
(A-Bank)
Read
CAc
11
12
(B-Bank)
CBd
Read
13
14
Publication Date : Jan. 2000
(A-Bank)
CAe
Read
15
16
M12L16161A
17
Revision : 1.3u
Precharge
(A-Bank)
*Note2
18
19
: Don't care