MTV230MF64 ETC1 [List of Unclassifed Manufacturers], MTV230MF64 Datasheet

no-image

MTV230MF64

Manufacturer Part Number
MTV230MF64
Description
8051 Embedded LCD Monitor Controller with Flash OSD
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
FEATURES
GENERAL DESCRIPTIONS
The MTV230M micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA
DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal
OSD character Flash-ROM.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.0
8051 core, 12MHz operating frequency with double CPU clock option, 3.3V power supply.
1024-byte RAM, 64K-byte program Flash-ROM.
Maximum 4 channels of 5V open-drain PWM DAC.
Maximum 32 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment.
Built-in low power reset circuit.
Compliant with VESA DDC2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
Maximum 4-channel 6-bit ADC.
Watchdog timer with programmable interval.
OSD controller features:
. Full-screen display consists of 15 (rows) by 30 (columns) characters.
. Programmable OSD menu positioning for display screen center.
. 512 Flash-ROM fonts, with 12x18 dot matrix, including 480 standard fonts and 32 multi-color fonts.
. Character (per row) and window intensity control.
. Character bordering, shadowing and blinking effect.
. Character height control (18 to 71 lines), double height and/or width control.
. 4 programmable windows with multi-level operation and programmable shadowing width/height/color.
In System Programming function (ISP).
42-pin SDIP or 44-pin PLCC/QFP package.
P1.0-7
P3.0-2
P3.4-5
P4.0-7
P5.0-7
RST
X1
X2
8051 Embedded LCD Monitor Controller
MYSON
TECHNOLOGY
CORE
8051
P0.0-7
P2.0-3
INT1
ALE
WR
RD
with Flash OSD
P0.0-7
P2.0-3
RD
WR
ALE
INT1
AD0-3
PWM DAC
DA0-3
- 1 -
XFR
ADC
CONTROL
CONTROL
INTERFACE
H/VSYNC
DDC & IIC
OSD
MTV230M
HBLANK
VBLANK
(Rev 1.0)
HSYNC
VSYNC
OSDHS
OSDVS
GOUT
ROUT
BOUT
FBKG
HSDA
HSCL
ISDA
ISCL
XIN
INT
2000/11/15

Related parts for MTV230MF64

MTV230MF64 Summary of contents

Page 1

MYSON TECHNOLOGY 8051 Embedded LCD Monitor Controller FEATURES 8051 core, 12MHz operating frequency with double CPU clock option, 3.3V power supply. 1024-byte RAM, 64K-byte program Flash-ROM. Maximum 4 channels of 5V open-drain PWM DAC. Maximum 32 bi-directional I/O pins. SYNC ...

Page 2

MYSON TECHNOLOGY PIN CONNECTION P4.5 9 P4.4 10 P4.3 11 MTV230M P4 Pin P4.1/VSYNC 13 PLCC P4.0/HSYNC 14 P3.0/Rxd/HSCL 15 P3.1/Txd/HSDA 16 P3.2/INT0 17 Revision 1.0 ROUT 1 XIN 2 OSDHS 3 OSDVS 4 ...

Page 3

MYSON TECHNOLOGY PIN CONFIGURATION A “CMOS pin” can be used as Input or Output mode. To use these pins as output mode, S/W needs to set the corresponding output enable control bit “P xx oe” Otherwise, the “P ...

Page 4

MYSON TECHNOLOGY PIN DESCRIPTION #44/42 Name Type RST I 19 VDD - 18 VSS - P1.0 I/O 25 P1.1 I/O 26 P1.2 I/O 27 P1.3 I/O 28 P1.4 I/O 29 P1.5 I/O 30 P1.6 I/O ...

Page 5

MYSON TECHNOLOGY FUNCTIONAL DESCRIPTIONS 1. 8051 CPU Core The CPU core of MTV230M is compatible with the industry standard 8051, which includes 256 bytes RAM, Special Function Registers (SFR), two timers, five interrupt sources and serial interface. The CPU core ...

Page 6

MYSON TECHNOLOGY 3. Chip Configuration The Chip Configuration registers define the chip pins function, as well as the connection, configuration and frequency of the functional block. Reg name addr bit7 PADMOD F2Bh (w) HIICE PADMOD F2Ch (w) DA3E PADMOD F2Dh ...

Page 7

MYSON TECHNOLOGY = 0 P4.2 is input pin. P41oe = 1 P4.1 is output pin P4.1 is input pin. P40oe = 1 P4.0 is output pin P4.0 is input pin. P57oe = 1 P5.7 is output ...

Page 8

MYSON TECHNOLOGY to define whether these pins are input or output. Port6 is purely output. Reg name addr bit7 PORT4 F30h(r/w) PORT4 F31h(r/w) PORT4 F32h(r/w) PORT4 F33h(r/w) PORT4 F34h(r/w) PORT4 F35h(r/w) PORT4 F36h(r/w) PORT4 F37h(r/w) PORT5 F38h(r/w) PORT5 F39h(r/w) PORT5 ...

Page 9

MYSON TECHNOLOGY 6. H/V SYNC Processing The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC inputs presence check, frequency counting, polarity detection and H/V output polarity control. The present and frequency function block treat any pulse ...

Page 10

MYSON TECHNOLOGY 6.2.1 H-Freq Table H-Freq(KHZ 6.2.2 V-Freq Table V-Freq(Hz 6.3 H/V Present Check The Hpresent function checks the input HSYNC pulse, ...

Page 11

MYSON TECHNOLOGY 6.7 H/V SYNC Processor Register Reg name addr bit7 HVSTUS F40h (r) CVpre HCNTH F41h (r) Hovf HCNTL F42h (r) HF7 VCNTH F43h (r) Vovf VCNTL F44h (r) VF7 HVCTR0 F40h (w) C1 HVCTR3 F43h (w) INTFLG F48h ...

Page 12

MYSON TECHNOLOGY = 0 Positive polarity VBLANK output. HVCTR3 (w) : HSYNC clamp pulse control register. CLPEG = 1 Clamp pulse follows HSYNC leading edge Clamp pulse follows HSYNC trailing edge. CLPPO = 1 Positive polarity clamp pulse ...

Page 13

MYSON TECHNOLOGY LSB "xx" in XFR. This feature enables MTV230M to meet PC99 requirement. 7.2 Slave Mode IIC Function Block The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using IIC protocol. ...

Page 14

MYSON TECHNOLOGY Reg name addr bit7 IICCTR F00h (r/w) IICSTUS F01h (r) WadrB IICSTUS F02h (r) MAckIn INTFLG F03h (r) TXBI INTFLG F03h (w) INTEN F04h (w) ETXBI MBUF F05h (r/w) RCABUF F06h (r) TXABUF F06h (w) SLVAADR F07h (w) ...

Page 15

MYSON TECHNOLOGY MbufI = 1 Indicates a byte is sent/received to/from the master IIC bus. INTEN (w) : Interrupt enable. ETXBI = 1 Enables TXBBUF interrupt. ERCBI = 1 Enables RCBBUF interrupt. ESlvBMI = 1 Enables slave address B match ...

Page 16

MYSON TECHNOLOGY Reg name addr bit7 ADC F10h (w) ENADC ADC F10h (r) WDT F18h (w) WEN WDT (w) : Watchdog Timer control register. WEN = 1 WCLR = 1 WDT2: WDT0 = ...

Page 17

MYSON TECHNOLOGY mode. Command Write S-tttttt10k-cccccxxBk-AAAAAAAAk-P Command Read S-tttttt11k-cccccXXBK-AAAAAAAAK-aaaaaaaaK-RRRRRRRRK-rrrrrrrrK-P Data Write S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... –ddddddddk-ddddddddk-P Data Read S-tttttt00k-aaaaaaaak-(P)- S-tttttt01k-ddddddddK-ddddddddK- ... –ddddddddK-ddddddddK-P where S = start or re-start K = ack by host ( tttttt = ISP slave address B ...

Page 18

MYSON TECHNOLOGY S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... 10.4 ISP Data Read st nd The 1 and 2 byte are the same as “Data write” to define the low address of Flash. Between 2 bytes, the ISP host may issue Stop-Start or only Re-Start. ...

Page 19

MYSON TECHNOLOGY shown in the table below. The programmable vertical size ranges are 270 lines to maximum 2130 lines. The vertical display center for full screen display could be figured out according to the information of vertical starting position register ...

Page 20

MYSON TECHNOLOGY To program ADDRESS bytes and ATTRIBUTE bytes of the display RAM: Step 1. Write data into OSDRA to determine the programming row address of the display RAM. And define whether it is the row address of ADDRESS byte ...

Page 21

MYSON TECHNOLOGY Row # (OSDRA ADDRESS bytes: Display characters address (OSDRA 0 ~ 14, OSDCA MSB CRADDR : Defines Flash-ROM OSD character address from address 0 to 511. (a) ...

Page 22

MYSON TECHNOLOGY R/G/B dot pattern is output to corresponding R/G/B output. See figure below for the sample displayed color font. Note: No black color can defined in color font, black window or background underline the color font can make the ...

Page 23

MYSON TECHNOLOGY 11.8 OSD Processor registers Reg name addr bit7 OSDRA FA0h (w) A1 OSDCA FA1h (w) OSDDT0 FA2h (w) D7 OSDDT1 FA3h (w) D7 W1ROW FC0h (w) W1COL FC1h (w) W1COL FC2h (w) W2ROW FC3h (w) W2COL FC4h (w) ...

Page 24

MYSON TECHNOLOGY WINT : Specifies the color intensity of the background window 1. Setting this bit to “0” means low intensity. WSHD : Enables shadowing on the window Specifies the color of the relative background ...

Page 25

MYSON TECHNOLOGY turned on from off state or vice versa Disables the fade-in/fade-out and blending-in/blending-out effect. Blend = 1 Selects the blending-in/blending-out effect if FBEN bit is set to “1” Selects the fade-in/fade-out effect if FBEN ...

Page 26

MYSON TECHNOLOGY Bordering Shadowing Character Bordering and Shadowing and Shadowing on Window WINSC (w) : Window shadowing color control registers. R1, G1 Define the shadowing color of window 1. R2, G2 Define the shadowing color of ...

Page 27

MYSON TECHNOLOGY Memory Map of XFR Reg name addr bit7 IICCTR F00h (r/w) IICSTUS F01h (r) WadrB IICSTUS F02h (r) MAckIn INTFLG F03h (r) TXBI INTFLG F03h (w) INTEN F04h (w) ETXBI MBUF F05h (r/w) RCABUF F06h (r) TXABUF F06h ...

Page 28

MYSON TECHNOLOGY VCNTH F43h (r) Vovf VCNTL F44h (r) VF7 HVCTR0 F40h (w) C1 HVCTR3 F43h (w) INTFLG F48h (r/w) HPRchg VPRchg HPLchg VPLchg INTEN F49h (w) EHPR OSDRA FA0h (w) A1 OSDCA FA1h (w) OSDDT0 FA2h (w) D7 OSDDT1 ...

Page 29

MYSON TECHNOLOGY ELECTRICAL PARAMETERS 1. Absolute Maximum Ratings at: Ta VSS=0V Name Maximum Supply Voltage Maximum Input Voltage (except Open Drain Pin)) Maximum Input Voltage (Open Drain pin) Maximum Operating Temperature Maximum Storage Temperature 2. ...

Page 30

MYSON TECHNOLOGY SCL low time START condition setup time START condition hold time STOP condition setup time STOP condition hold time t SCKH t SU:STA t HD:STA PACKAGE DIMENSION 1. 42 pin SDIP Unit: mm Revision 1.0 tSCLL tSU:STA tHD:STA ...

Page 31

MYSON TECHNOLOGY 2. 44 pin PLCC Unit: PIN #1 HOLE 0 0.045*45 0.050 TYP. 0.026~0.032 TYP. 0.653 +/-0.003 0.690 +/-0.005 Ordering Information Standard Configurations: Prefix Part Type MTV 230M Part Numbers: Prefix Part Type MTV 230M MTV 230M Revision 1.0 ...

Related keywords