MTV230MF64 ETC1 [List of Unclassifed Manufacturers], MTV230MF64 Datasheet - Page 23

• Manufacturer Part Number: MTV230MF64
• Description: 8051 Embedded LCD Monitor Controller with Flash OSD
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

11.8 OSD Processor registers
OSDRA (w) :
OSDCA (w) : This is the column address of the display RAM that next 9-bit data should be written into.
OSDDT0 (w) : The MSB (bit 8) = 0, 8 LSB (bit 7 ~ bit 0) = OSDDT0. The 9-bit data will be written into current
OSDDT1 (w) : The MSB (bit 8) = 1, 8 LSB (bit 7 ~ bit 0) = OSDDT1. The 9-bit data will be written into current
W1ROW, W1COL (w) : Window 1 control registers.
Revision 1.0
Reg name
OSDCON
OSDCON
RSPACE
OSDDT0
OSDDT1
W1ROW
W2ROW
W3ROW
W4ROW
W1COL
W1COL
W2COL
W2COL
W3COL
W3COL
W4COL
W4COL
OSDRA
OSDCA
WINSW
VERTD
WINSH
WINSC
WINSC
FSSTP
HORD
CHSC
XDEL
CH
Row (column) start (end) address : These registers are used to specify the window 1 size. It should
R3-R0 : This is the row address of the display RAM that next 9-bit data should be written into.
A1-A0 = (0, 0)
WEN :
FD1h (r/w) OSDEN
FD2h (r/w)
(OSDRA, OSDCA) address of the display RAM. It will also trigger the post increment
operation of OSDRA and OSDCA.
(OSDRA, OSDCA) address of the display RAM. It will also trigger the post increment
operation of OSDRA and OSDCA.
FCCh (w)
FCDh (w)
FCAh (w)
FCBh (w)
FCEh (w)
FA0h (w)
FA1h (w)
FA2h (w)
FA3h (w)
FC0h (w)
FC1h (w)
FC2h (w)
FC3h (w)
FC4h (w)
FC5h (w)
FC6h (w)
FC7h (w)
FC8h (w)
FC9h (w)
FD0h (w)
FD3h (w)
FD4h (w)
FD5h (w)
FD6h (w)
FD7h (w)
FD8h (w)
FD9h (w)
= (0, 1)
addr
Enables the relative background window 1 display.
MYSON
TECHNOLOGY
WW41
WH41
FSW
bit7
D7
D7
A1
Next 9-bit data will be written into ADDRESS byte.
Next 9-bit data will be written into ATTRIBUTE byte.
-
-
-
-
-
-
-
Row start address
Row start address
Row start address
Row start address
WW40
BSEN
WH40
bit6
D6
D6
R1
R3
A0
Column start address
Column start address
Column start address
Column start address
-
-
-
-
-
Column end address
Column end address
Column end address
Column end address
be noted that when the start address is greater than end address,
the corresponding window display will be disabled.
Shadow
WW31
WH31
bit5
D5
D5
G1
G3
-
-
-
-
-
-
- 23 -
WW30
WH30
FBEN
Horizontal delay
DWE
bit4
Vertical delay
C4
D4
D4
B1
B3
-
-
-
Character height
WW21
WH21
Blend
HSP
bit3
R3
C3
D3
D3
-
-
-
-
Row to row spacing
WENclr
Row end address
Row end address
Row end address
Row end address
WW20
WH20
WEN
WEN
WEN
WEN
CSR
VSP
FSR
bit2
R2
C2
D2
D2
R2
R4
D2
R
R
R
R
RAMclr
WW11
MTV230M
WH11
WINT
WINT
WINT
WINT
CSG
FSG
bit1
G2
G4
R1
C1
D1
D1
D1
G
G
G
G
-
(Rev 1.0)
FBKGC
WSHD
WSHD
WSHD
WSHD
WW10
2000/11/15
WH10
CSB
FSB
bit0
R0
C0
D0
D0
B2
B4
D0
B
B
B
B
-