MTV230MF64 ETC1 [List of Unclassifed Manufacturers], MTV230MF64 Datasheet - Page 16

• Manufacturer Part Number: MTV230MF64
• Description: 8051 Embedded LCD Monitor Controller with Flash OSD
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

WDT (w) :
ADC (w) :
ADC (r) :
10. In System Programming function (ISP)
The two Flash memories (OSD Flash and Code Flash) can be programmed by a specific WRITER in parallel
mode, or by IIC Host in serial mode while the system is working. The feature of ISP is outlined as below:
After power on/Reset, The MTV230M is running the original Program Code. Once the S/W detects an ISP
request (by key or IIC), S/W can accept the request following the steps below:
When ISP is enabled, the MTV230M will disable Watchdog reset and switch the Flash interface to ISP host
in 15-22.5uS. So S/W MUST enter idle mode immediately after enabling ISP. In the 8051 idle mode, PWM
DACs and I/O pins keep running at its former status. There are 4 types of IIC bus transfer protocols in ISP
Revision 1.0
Reg name
WDT
ADC
ADC
WEN
WCLR
WDT2: WDT0 = 0
ENADC
SADC0
SADC1
SADC2
SADC3
1. Single 3.3V power supply for Program/Erase/Verify.
2. Block Erase: 512 Byte for Program Code or 256 words for OSD fonts, both are 10mS time.
3. Whole Flash erase (Blank): 10mS
4. Byte/Word programming Cycle time: 60uS per byte, 120uS per word
5. Read access time: 40ns
6. Only one two-pin IIC bus (shared with DDC2) is needed for ISP in user/factory mode.
7. IIC Bus clock rates up to 140KHz.
8. Whole 64K-byte/9K-word Flash programming within 6/2 Sec.
9. CRC check provides 100% coverage for all single/double bit errors.
1. Clear watchdog to prevent reset during ISP period.
2. Disable all interrupt to prevent CPU wake-up.
3. Write IIC address of ISP slave to ISPSLV for communication.
4. Write 93h to ISP enable register (ISPEN) to enable ISP.
5. Enter 8051 idle mode.
F10h (w) ENADC
F18h (w)
F10h (r)
Watchdog Timer control register.
ADC control.
ADC converts result.
addr
MYSON
TECHNOLOGY
= 1
= 1
= 1
= 2
= 3
= 4
= 5
= 6
= 7
= 1
= 1
= 1
= 1
= 1
WEN
bit7
Enables Watchdog Timer.
Clears Watchdog Timer.
Overflow interval = 8 x 0.25 sec.
Overflow interval = 1 x 0.25 sec.
Overflow interval = 2 x 0.25 sec.
Overflow interval = 3 x 0.25 sec.
Overflow interval = 4 x 0.25 sec.
Overflow interval = 5 x 0.25 sec.
Overflow interval = 6 x 0.25 sec.
Overflow interval = 7 x 0.25 sec.
Enables ADC.
Selects ADC0 pin input.
Selects ADC1 pin input.
Selects ADC2 pin input.
Selects ADC3 pin input.
WCLR
bit6
bit5
- 16 -
bit4
ADC convert Result
SADC3
bit3
SADC2
WDT2
bit2
SADC1
MTV230M
WDT1
bit1
(Rev 1.0)
SADC0
WDT0
2000/11/15
bit0