9248AG-192LFT Integrated Device Technology, 9248AG-192LFT Datasheet - Page 2

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9248AG-192LFT

Manufacturer Part Number
9248AG-192LFT
Description
ic,9248ag-192lft
Manufacturer
Integrated Device Technology
Datasheet
ICS9248-192
0540F—10/27/05
Pin Descriptions
12, 11, 10, 7, 6, 5
Pin number
15
13
14
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
8
9
PCICLK (5:0)
CPU3.3-2.5#
CPU_STOP#
SEL 66/60#
Sel48_24#
24_48MHz
VDD_Core
GND_Core
GNDLCPU
PCI_Stop#
VDDLCPU
CPUCLK0
Pin name
GNDREF
VDDREF
GNDPCI
VDDPCI
SDATA
GND48
VDD48
48MHz
SCLK
PD#
REF
X1
X2
Power
Output
Output
Power
Power
Output
Output
Power
Power
Power
Power
Output
Power
Power
Output
Power
Type
Input
Input
Input
Input
Input
Input
Input
I/O
IN
Ground for 14.318 MHz reference clock outputs
14.318 MHz crystal input
14.318 MHz crystal output
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
3.3V PCI clock outputs, free running selectable
Ground for PCI clock outputs
3.3V power for the PCI clock outputs
Selects 24MHz (0) or 48MHz (1) output
Selectable output either 24MHz or 48MHz
Data pin for I
Clock pin of I
3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor.
3.3V 48 MHz clock output, fixed frequency clock typically used with
USB devices
Ground for 48 MHz clocks
3.3V power for 48/24 MHz clocks
Control for the frequency of clocks at the
CPU & PCICLK output pins.
"0" = 60 MHz. "1" = 66.6 MHz.
The PCI clock is multiplexed to run at 33.3 MHz
for both selected cases.
Isolated 3.3V power for core
Isolated ground for core
Synchronous active low input used to stop the PCICLK in active low
state. It will not effect PCICLK_F or any other outputs.
CPU clock outputs selectable 2.5V or 3.3V.
Ground for CPU clock outputs
2.5V or 3.3V power for CPU clock outputs
Asynchronous active low input pin used to stop the CPUCLK in
active low state, all other clocks will continue to run. The CPUCLK
will have a "Turnon " latency of at least 3 CPU clocks.
3.3V 14.318 MHz reference clock output
3.3V power for 14.318 MHz reference clock outputs.
2
2
2
C circuitry 5V tolerant
C circuitry 5V tolerant
Description

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