9248AF-128LF Integrated Device Technology, 9248AF-128LF Datasheet
9248AF-128LF
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9248AF-128LF Summary of contents
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Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers Recommended Application: SIS 530/620 style chipset Output Features: • CPU @ 2.5V/3. 133.3 MHz. • PCI @ 3.3V (including 1 free-running) • SDRAMs ...
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ICS9248-128 Pin Descriptions P in number P in name 1 V DDR 1 ode 3,9,16,22, GND 27,33, 6,14 V DDP 1 CICLK _F P CICLK ...
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General Description The ICS9248-128 is the single chip clock solution for Desktop/Notebook designs using the SIS style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without ...
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ICS9248-128 Serial Configuration Command Bitmap Byte 0: Functionality and frequency select register (Default = ± ...
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Byte 1: CPU, Active/Inactive Register (1 = enable disable ...
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ICS9248-128 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . ...
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Electrical Characteristics - CPUCLK 70º 3.3 V +/-5 DDL PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low ...
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ICS9248-128 Electrical Characteristics - PCICLK 70º 3.3 V +/- 5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current ...
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Electrical Characteristics - REF/48MHz/SIO 70º 3.3 V +/- 5 PARAMETER SYMBOL Output High V OH5 Voltage Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I ...
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ICS9248-128 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS ...
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CPU_STOP# Timing Diagram CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-128. The minimum that the CPU clock is enabled (CPU_STOP# ...
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ICS9248-128 SDRAM_STOP# Timing Diagram SDRAM_STOP sychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. SDRAM_STOP# is synchronized by the ICS9248-128. All other clocks will continue to run while ...
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PCI_STOP# Timing Diagram PCI_STOP synchronous input to the ICS9248-128 used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-128 internally. The minimum that the PCICLK (0:4) clocks are ...
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ICS9248-128 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 128 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present ...
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General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance. Notes: ...
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ICS9248-128 Ordering Information ICS9248yF-128 Example: ICS XXXX PPP Pattern Number ( digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists digit numbers) Prefix ICS, ...