9248AF-128LF Integrated Device Technology, 9248AF-128LF Datasheet - Page 12

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9248AF-128LF

Manufacturer Part Number
9248AF-128LF
Description
Manufacturer
Integrated Device Technology
Datasheet
SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
SDRAM_STOP# is synchronized by the ICS9248-128. All other clocks will continue to run while the SDRAM clocks are
disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse
width is a full pulse.
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SDRAM_STOP# Timing Diagram
ICS9248-128
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
3. All other clocks continue to run undisturbed.
the SDRAM clocks inside the ICS9248-128.
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