9248AF-128LF Integrated Device Technology, 9248AF-128LF Datasheet - Page 2

• Manufacturer Part Number: 9248AF-128LF
• Manufacturer: Integrated Device Technology

Pin Descriptions
Notes:
1:
2:
Third party brands and names are the property of their respective owners.
ICS9248-128
15,28,29,31,32,
P in number
13, 12, 11, 10
34,35,37,38
3,9,16,22,
to program logic Hi to VDD or GND for logic low.
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
27,33,39
40,41,43
25
26
30,36
44
46
6,14
17
18
20
21
2
7
8
19
23
24
42
45
47
48
1
4
5
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
S DRA M _S TOP #
CP UCLK (3:1)
P CICLK (4:1)
S DRA M (7:0)
CP U_S TOP #
CP U3.3#_2.5
P in name
S DRA M 12,
P CI-S TOP #
S E L24_14#
S DRA M 11
S DRA M 10
V DDLA P IC
P CICLK _F
V DDLCP U
P CICLK 0
V DDS D/C
S DRA M 9
S DRA M 8
S D_S E L#
V DDS DR
V DDR/X
V DDP CI
48 M Hz
IOA P IC
S DA TA
GNDL
RE F0
S CLK
RE F2
RE F1
M ode
GND
P D#
FS 1
FS 2
S IO
FS 0
X 1
X 2
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
P ower
P ower
P ower
P ower
P ower
0utput
P ower
P ower
P ower
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Is olated 3.3 V power for crys tal & referenc e
3.3V , 14.318 M Hz referenc e clock output.
Function s elec t pin, 1= des k top m ode, 0= m obile m ode. Latc hed input.
3.3 V Ground
14.318 M Hz crys tal input
14.318 M Hz crys tal output
3.3 V power for the P CI clock outputs
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V free running P CI c loc k output, will not be stopped by the P CI_S TOP #
3.3 V P CI cloc k outputs, generating tim ing requirem ents for P entium II
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V P CI cloc k outputs, generating tim ing requirem ents for P entium II
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
A s ynchronous ac tiv e low input pin used to s top the CP UCLK in low state,
all other cloc ks will c ontinue to run. The CP UCLK will have a "Turnon" latency
of at least 3 CP U clock s.
S DRA M c lock outputs . Frequency is s elec ted by S D-S E L latched input.
S y nc hronous active low input used to s top the PCICLK in a low state. It will not
effect P CICLK _F or any other outputs.
3.3 V power for S DRA M outputs and c ore
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
A s ynchronous ac tiv e low input us ed to stop the S DRA M in a low s tate.
It will not effec t any other outputs.
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
A s ynchronous ac tiv e low input pin used to power down the devic e into a low
power state. The internal c lock s are dis abled and the V CO and the c ry stal are
stopped. The latenc y of the power down will not be greater than 3m s .
Data input for I
Clock input of I
This input pin controls the frequency of the S IO. If logic 0 at power on
S IO= 14.318 M Hz . If logic 1 at power-on S IO= 24M Hz .
S uper I/O output. 24 or 14.318 M Hz. S electable at power-up by S E L24_14M Hz
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V 48 M Hz c lock output, fixed frequenc y cloc k ty pic ally us ed with
US B dev ices
3.3 V power for S DRA M outputs
2.5 V CPU and Host c loc k outputs
2.5 V power for CP U
3.3V , 14.318 M Hz referenc e clock output.
This pin selects the operating voltage for the CP U. If logic 0 at power on
CP U= 3.3 V and if logic 1 at power on CP U= 2.5 V operating voltage.
2.5 V Ground for the IOA P IC or CP U
3.3V , 14.318 M Hz referenc e clock output.
This input pin controls the frequency of the S DRA M .
2.5V fixed 14.318 M Hz IOA P IC clock outputs
2.5 V power for IOA P IC
D escription
2
2
2
C serial input.
C input