LCMXO2280E-5BN256C Lattice, LCMXO2280E-5BN256C Datasheet - Page 28

• Manufacturer Part Number: LCMXO2280E-5BN256C
• Description: CPLD - Complex Programmable Logic Devices 2280 LUTs 211 I/O 1.2V -5 SPD
• Manufacturer: Lattice

Specifications of LCMXO2280E-5BN256C

• Rohs: yes
• Memory Type: SRAM
• Number Of Macrocells: 1140
• Delay Time: 3.6 ns
• Number Of Programmable I/os: 211
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: CABGA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 595
• Supply Current: 20 mA
• Supply Voltage - Max: 1.26 V
• Supply Voltage - Min: 1.14 V

6.0 MachXO2 Soft Error Rate Data
Soft Error Rate (SER) testing is conducted to characterize the sensitivity of SRAM storage and device logic
elements to High Energy Neutron and Alpha Particle radiation. Charge induced by the impact of these particles
can collect at sensitive nodes in the device, and result in changes in the internal electrical states of the device.
While these changes do not cause physical damage to the device, they can cause a logical error in device
operation.
Neutron SRAM SER Rate – This characteristic is the rate of upset of Configuration RAM and Embedded Block
RAM (EBR) cells during neutron testing. Devices were configured with a logic pattern, exposed to measured
neutron doses, and the device configuration was read back from the device. Changed bits are identified through
pattern comparison. Neutron testing is normalized to the published neutron flux rate for New York City at sea
level. This rate is measured as Failures in Time (FITs) normalized per million bits in the device to allow for
translation across the device families densities.
Alpha SRAM SER Rate – This characteristic is the rate of upset of Configuration RAM and Embedded Block
RAM (EBR) cells during Alpha particle testing. Devices were configured with a logic pattern, exposed for a fixed
time period to a calibrated Alpha particle source, and the device configuration was read back from the device.
Changed bits are identified through pattern comparison. Alpha particle testing is normalized to a background
rate of 0.001Alpha/cm2-hr based on characterization of packaging materials. This rate is measured at Failures
in Time (FITs) normalized per million bits in the device to allow for translation across the device families
densities as Failures in Time (FITs) normalized per million bits in the device to allow for translation across the
device families densities.
All testing conforms to JEDEC JESD-89.
Table 6.1 - MachXO2 MEASURED FITs / Mb
* The EBR SER data was taken on the ECP3. The ECP3 shares the same base technology and SRAM cell.
Note: Detailed MachXO2 and ECP3 SER reports are available upon request. Lattice Semiconductor Corporation documents #25-106920
and #25-106669 respectively.
INDEX Return
High Energy Neutron
Stress / Structure
Alpha Particle
Configuration RAM
Configuration RAM
SRAM Type
* EBR
* EBR
28
Measured Fuses
Lattice Semiconductor Corporation Doc. #25-106923 Rev. F
MachXO2
359,640
359,640
73,728
73,728
Failures in Time
per Megabit
(FITs/Mb)
363
611
128
363